Monday 27 June 2016

COLLABORATECOM 2016: Call for Papers

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12th EAI International Conference on Collaborative Computing: Networking, Applications and Worksharing (CollaborateCom 2016)

November 12–13, 2016 | Beijing, People's Republic of China

---------------------------
CALL FOR PAPERS
---------------------------
12th EAI International Conference on Collaborative Computing: Networking, Applications and Worksharing  (CollaborateCom 2016) will be held in Beijing, China, and continue to serve as a premier international forum for discussion among academic and industrial researchers, practitioners, and students interested in collaborative networking, technology and systems, and applications.

Topics of interest include, but are not limited to:
·         Participatory sensing, crowdsourcing, and citizen science
·         Architectures, protocols, and enabling technologies for collaborative computing networks and systems
·         Autonomic computing and quality of services in collaborative networks, systems, and applications
·         Collaboration in pervasive and cloud computing environments
·         Collaboration in data-intensive scientific discovery
·         Collaboration in social media
·         Big data and spatio-temporal data in collaborative environments/systems
·         Collaboration techniques in data-intensive computing and cloud computing
·         Collaborative e-education, e-learning, and collaborative computing in large scale digital libraries
·         Collaboration in health-care environments
·         Collaborative information seeking
·         Collaborative mobile networks and infrastructures
·         Collaborative technologies for fast creation and deployment of new mobile services
·         Collaborative sensor networks, unmanned air and ground vehicle networks and applications
·         Collaborative, context-aware infrastructure
·         Collaborative, location-aware mobile systems/applications
·         Computer supported collaborative work with distributed systems
·         Cyber-physical systems
·         Distributed collaborative workflows
·         Data management and middleware support for collaborative information systems
·         Energy management for collaborative networks
·         Group-driven composition of systems from components
·         Human-centric ubiquitous collaboration
·         Human-robot collaboration
·         Internet of Things (IoT) and collaboration
·         Methodologies and tools for design and analysis of collaborative user applications
·         Models and mechanisms for real-time collaboration
·         Multi-agent technology and software technologies for collaborative networking and applications
·         Peer-to-peer and overlay networks, systems, and applications
·         Security, privacy and trust management in collaborative networks, systems, and applications
·         Simulation, performance evaluation, experiments, and case studies of collaborative networks and applications
·         Software design, testing, and experimentation technology for collaborative networking and applications
·         Theoretical foundations and algorithms for collaborative networks, applications, and worksharing
·         Tools for collaborative decision making processes
·         Trustworthy collaborative business processing in virtual organizations
·         Visualization techniques, interaction devices and visual languages for collaborative networks and applications
·         Web services technologies and service-oriented architectures for collaborative networking and applications
·         Workflow management for collaborative networks/systems

----------------------------
IMPORTANT DATES
----------------------------
Full Paper Submission deadline: 15 July 2016
Notification and Registration opens: 16 August 2016
Camera-ready deadline: 10 September 2016

---------------------------------------------
SUBMISSION and PUBLICATION
---------------------------------------------
Papers should be submitted through EAI 'Confy' system, and have to comply with the SPRINGER format

The proceedings are submitted for inclusion to the leading indexing services: DBLP, Google Scholar, Thomson Scientific ISI Proceedings, EI Elsevier Engineering Index, CrossRef, Scopus, as well as ICST's own EU Digital Library (EUDL).

Regular papers should be up to 10 pages in length.
Short papers should be up to 6 pages in length.

Please visit the COLLABORATECOM 2016 website http://collaboratecom.org/2016/show/initial-submission for author instructions.

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Call For Papers: ESPM2 2016@SC'16 - Second International Workshop on Extreme Scale Programming Models and Middleware

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================================================================================================
ESPM2 2016: Second International Workshop on Extreme Scale Programming Models and Middleware

In conjunction with the International Conference on High Performance Computing, Networking, Storage and Analysis (SC’16), Salt Lake City, Utah, USA, Friday, November 18th, 2016
Held in cooperation with ACM SIGHPC
================================================================================================================
Next generation architectures and systems being deployed are characterized by high concurrency, low memory per-core, and multiple levels of hierarchy and heterogeneity. These characteristics bring out new challenges in energy efficiency, fault-tolerance and scalability. It is commonly believed that software has the biggest share of the responsibility to tackle these challenges. In other words, this responsibility is delegated to the next generation programming models and their associated middleware/runtimes. ESPM2 focuses on different aspects of programming models such as task-based parallelism (X10, OCR, Habanero, Legion, Charm++, HPX), PGAS (OpenSHMEM, UPC, UPC++, CAF, Chapel, etc.), Directive-based languages (OpenMP, OpenACC), Accelerator programming (CUDA, OpenCL), Hybrid MPI+X, etc. It also focuses on their associated middleware (unified runtimes, interoperability for hybrid programming, tight integration of MPI+X, and support for accelerators) for next generation systems and architectures. The objective of ESPM2 workshop is to serve as a forum that brings together scientists, researchers and software/hardware designers from academia, industry and national laboratories to share their knowledge and experience and to learn the opportunities and challenges in designing programming models, runtime systems, compilers and languages for next-generation HPC Systems and applications.
The Second ESPM2 workshop, to be held with the Supercomputing (SC'2016) conference in Salt Lake City, Texas, will serve as an event for discussion in the areas of programming models and runtimes, language design, compilers, and application development. It will provide a timely meeting for scientists and engineers to present the latest ideas and findings in these rapidly evolving areas. The workshop will particularly focus on innovative approaches in the areas of emerging programming models for large- scale parallel systems and many-core architectures. Topics of interest for the ESPM2 workshop include (but are not limited to):
  • New programming models, languages and constructs for exploiting high concurrency and heterogeneity
  • Experience with and improvements for existing parallel languages and run-time environments such as:
           o MPI
           o PGAS (UPC, OpenSHMEM, Chapel, CAF, UPC++...)
           o Directive-based programming (OpenMP, OpenACC..)
           o Asynchronous Task-based models (X10, OCR, Habanero, Legion, Charm++, HPX) and
           o Hybrid MPI+X models
  • Parallel compilers, programming tools, and environments
  • Software and system support for extreme scalability including fault tolerance
  • Programming environments for heterogeneous multi-core systems and accelerators such as KNC, KNL, ARM, GPUs, FPGAs, MICs and DSPs
Papers should present original research and should provide sufficient background material to make them accessible to the broader community.
Important Dates
Technical paper submission deadline: August 26th 2016 (11:59 PM, EST)
Author notification:                             October 7th 2016
Camera-ready deadline:                       September 30th, 2016 
Workshop:                                            November 18th, 2016
Submission
Abstracts and papers need to be submitted via the EasyChair conference system. (https://easychair.org/conferences/?conf=espm22016)
Submissions are accepted under the following two categories:
  • Full Paper: Should not exceed 8 pages using ACM format with 10pt font. Each submission must be a single PDF file.
  • Short Paper: Should not exceed 4 pages using ACM format with 10pt font. Each submission must be a single PDF file.
    Submissions must be ACM formatted:
  • ACM SigHPC will publish the workshop proceedings which will be available through the ACM Digital Library
  • The papers must contain original content and should not have been previously published or submitted to a peer-reviewed journal/conference
  • Papers must be submitted in PDF format (readable by Adobe Acrobat Reader 5.0 and higher) and formatted for 8.5" x 11" (U.S. Letter).
  • The manuscript should be formatted according to ACM format (see http://www.acm.org/sigs/publications/proceedings-templates)
At least one of the authors of each accepted paper must register as a participant of the workshop and present the paper at the workshop, in order to have the paper published in the proceedings.
Organizing Committee Program Chairs
Khaled Hamidouche, The Ohio State University
Karl Schulz, Intel Corporation
Hari Subramoni, The Ohio State University
Dhabaleswar K. (DK) Panda, The Ohio State University
Program Committee
Francois Bodin, University of Rennes and INRIA, France 
Guang R. Gao, University of Delaware
Vladimir Getov, University of Westminster, UK
Jeff Hammond, Intel Labs
Zhigang Huo, Institute of Computing Technology, Chinese Academy of Sciences, China
Darren Kerbyson, Pacific Northwest National Laboratory 
Olivier Tardieu, IBM T.J Watson Research Center
Rajeev Thakur, Argonne National Laboratory
Abhinav Vishnu, Pacific Northwest National Laboratory

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Thursday 23 June 2016

CFP: 3nd International Workshop on Innovating the Network for Data Intensive Science (INDIS) 2016 @SC16 Deadline: Aug. 21

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*/SC16: INDIS Workshop Call for Papers/*

*/ /*

*Innovating the Network for Data Intensive Science (INDIS)*



The 3nd International Workshop on Innovating the Network for Data
Intensive Science (INDIS) 2016, in conjunction with SC16: IEEE/ACM
International Conference for High Performance Computing, Networking,
Storage and Analysis, in Salt Lake City, Utah, on November 13, 2016,
9h00 – 17h00.



Call for papers:

We invite full original papers to be submitted via the FGCS submission
system.

·      On-line Journal:
http://www.sciencedirect.com/science/journal/0167739X

·      Journal Description: http://www.elsevier.com/locate/fgcs

·      Electronic Submission: http://ees.elsevier.com/fgcs



Workshop website: https://scinet.supercomputing.org/workshop/

Note also the call for Network Research Environment demos on the SCinet
website!

* *

*Workshop Scope*:



Science is making the transition from Data-poor to Data-rich. Where in
the past only limited experimental data was compared to big amounts of
simulation-generated data at Supercomputing centers, we now see those
centers transform into big data stream processing nodes. Wide area
networks are now an integral and essential part of the data driven
Supercomputing ecosystem connecting information-sources, data-stores,
processing, simulation, and visualization and user communities together.
Further networks are required to connect research instruments such as
photon sources, and large visualization displays.



Networks for data-intensive science have more extreme requirements than
general-purpose networks.  These requirements closely impact the design
of processor interconnects in supercomputers/cluster computers, but they
also impact campus networks, regional networks and national backbone
networks.



The developments in network technology are tremendous. Speeds of many
100’s of Gigabit and deep programmability of network infrastructure are
now common. This enables a fundamentally different approach of
integrating networks in Supercomputing applications.



This workshop encourages research papers that address one or more of
these needs that are essential in the scientific discovery process. This
workshop will also serve as a platform for participants in SCinet to
present experimental papers on their latest designs and solutions.
SCinet is the high-speed network engine of the SC conference. This
network is state of the art, connects many demonstrators of big science
data processing infrastructures at the highest line speeds, deploys the
newest technologies available, and demonstrates novel functionality. The
show floor network connects to many laboratories and universities
worldwide using high-bandwidth connections.



This workshop brings together SCinet engineers and network researchers
to share challenges and potential solutions. Their novel ideas will
allow future SCinets to stretch their deployed technologies and further
drive new network research. We invite papers that propose new and novel
techniques that increase the capacity and functionality of scientific
computing and wide-area networks.



*Topics of interest include but are not limited to:*

·      High-speed network protocols

·      Network architectures

·      Securing high-speed networks

·      High performance data transfer applications and techniques

·      Science DMZs and other campus network constructs

·      Software-defined networking , OpenFlow and NFV

·      Optical networking

·      Network monitoring and traffic analytics

·      Requirements and issues for network quality of service (QoS)

·      HPC interconnects: topologies and protocols for supercomputers
and cluster computers

·      Storage area networks

·      Network management: diagnostics, troubleshooting, fault
management, performance monitoring, configuration management

·      Multi-domain networking

*Important Dates:*

Paper Submission due:                    August 21, 2016

Notification of acceptance:               October 1, 2016

Workshop-Ready version due:        November 1, 2016

Workshop Date:                                November 13, 2016

Camera-Ready version due:            January 15, 2017



*Submission Guidelines:*

Authors should prepare their manuscript according to the Guide for
Authors available from the online submission page of the Future
Generation Computer Systems at http://ees.elsevier.com/fgcs/ .

Authors should select “SI: SC16 - INDIS” when they reach the “Article
Type” step in the submission process. Reviewing of the full papers will
be done by the program committee.  At least one of the authors of an
accepted paper should register and present the paper.  Accepted papers
will be included in the proceedings and will be available through
Elsevier FGCS.



*Registration*:  SC'16 workshop registration is handled through the
SC'16 system. Please visit http://sc16.supercomputing.org for more
information.

If you have any further questions, please email:

scinet-workshop@scinet.supercomputing.org
<mailto:scinet-workshop@scinet.supercomputing.org>



*Workshop Organizers:*

·       *Cees de Laat:*Professor System and Network Engineering,
University of Amsterdam, The Netherlands.

·       *Brian L. Tierney:*Staff Scientist and Group Leader of the ESnet
Advanced Network Technologies Group at Lawrence Berkeley National
Laboratory.

·       *Paola Grosso: *Assistant professor in the System and Network
Engineering (SNE) group at the University of Amsterdam, The Netherlands.

·       *Malathi Veeraraghavan*: Professor, Charles L. Brown Dept. of
Electrical and Computer Engineering, and Associate Director,
Infrastructure and Services, Data Science Institute, University of Virginia.

*Liaisons:*

·       *Mehmet Balman:*Liaison to the NDM committee, VMware Inc. &
Lawrence Berkeley National Laboratory, USA.

·       *Sylvia Kuijpers*: Liaison to communications, SURFnet, The
Netherlands, SCinet team-member INDIS.



*Program Committee*:

·       Pavan Balaji, Argonne National Laboratory and Northwestern
University, USA

·       Mehmet Balman, VMware Inc. & Lawrence Berkeley National
Laboratory, USA

·       Virginia Bedford, US Army Corps of Engineers, USA

·       Surendra Byna, Lawrence Berkeley National Laboratory, USA

·       Jerry Chou, National Tsing Hua University, Taiwan

·       Zhihui Du, Tsinghua University, China

·       Kartik Gopalan, State University of New York at Binghamton, USA

·       Paola Grosso, University of Amsterdam, The Netherlands.

·       Zhiyi Huang, University of Otago, New Zealand

·       Raj Kettimuthu, Argonne National Laboratory and University of
Chicago, USA

·       Cees de Laat, University of Amsterdam, The Netherlands.

·       Jinoh Kim, Texas A&M University-Commerce, USA

·       Siva Kulasekaran, Texas Advanced Computing Center, USA

·       Kate Mace, ESnet, USA

·       Manish Parashar, Rutgers University, USA

·       Eric Pouyoul, Energy Sciences Network and Lawrence Berkeley Lab,
USA

·       Corby Schmitz, Argonne National Lab/ Loyola University, Chicago,
USA

·       Jennifer Schopf, Indiana University, USA

·       Martin Swany, Indiana University, USA

·       Brian L. Tierney, ESnet, Lawrence Berkeley National Laboratory, USA

·       Malathi Veeraraghavan, University of Virginia, USA

·       Venkat Vishwanath, Argonne National Laboratory, USA

·       Linda Winkler, Arogonne National Lab

·       Wenji Wu, Fermilab, USA

·       Lei Xia, LinkedIn, USA

·       Esma Yildirim, Fatih University, Turkey

·       Yufei Ren,  IBM, Watson, USA

·       Matthew J Zekauskas: Senior researcher, Internet2, USA



*** Please forward to anyone who might be interested ***

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Fwd: The 1st Ultrascale Computing for Early Researchers Workshop (UCER 2016) - Last Extension

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Call for Papers for the 16th the 1st Ultrascale Computing for Early Researchers Workshop (UCER 2016)

Held in conjunction with ICA3PP 2016

Granada, Spain
December 14-16, 2016

http://dps.uibk.ac.at/~juan/ucer/
Paper Submission Deadline: July 17th, 2016 (Last Extension)


The aim of this workshop is to give the opportunity to early researchers (PhD students or recent PhD graduates) to show their work related to Ultrascale Computing. Although a future technology, currently, many systems are being designed with the goal of being used in ultrascale systems. Many different subtopics are related in the exploration of system software and applications for enabling a sustainable development of future high-scale computing platforms. The tasks involved range from the analysis of the current state-of-the-art on sustainability in large-scale systems to the proposition of new tools that aim to improve computations on these systems. The topics addressed are, among others, HPC, distributed systems, and big data communities in cross cutting aspects like programmability, scalability, resilience, energy efficiency, and data management. To get the goal of ultrascale computation it is needed to explore new programming paradigms, runtimes, and middlewares to increase the productivity, scalability, and reliability of parallel and distributed programming. At the same time, the new magnitude of data and computations brings up as inevitability consequence the probability of failure, so any advance on resilient schedulers that handle errors reactive or proactive, monitoring and assessment of failures, and malleable applications that can adapt their resource usage at runtime are welcome. Other major challenges involved are the restructuring the Input/Output (I/O) stack, the advancing predictive and adaptive data management, and the concern about huge energy consumption as one of the major limitations. This topic also includes identifying applications, high-level algorithms, and services amenable to ultrascale systems and investigating the redesign and reprogramming efforts needed for applications to efficiently exploit ultrascale platforms while providing sustainability.

UCER 2016 welcomes original submissions that have not been published and that are not under review by another conference or journal. To respect the workshop's aim, at least one author has to be a PhD student or recent PhD graduate. All submitted papers will be peer-reviewed by UCER's technical program committee. All submissions will be evaluated on significance, presentation, and interest to the workshop attendees.

Scope and Interest
===================================

The program committee cordially invites any novel research ideas in the following (but not limited to) topics:

- Parallel and distributed systems for ultrascale computing, including, frameworks, engines or programming models.
- GPU and Heterogeneous computing
- Data management methods and techniques for ultrascale computing.
- Fault tolerance techniques.
- Energy efficiency: monitoring, evaluation, modelling.
- Load balancing and scheduling
- Applications suitable for ultrascale computing.

Journal Publication
===================================

Extended version of selected papers from the workshop will be invited by the UCER2016 program committee for publication, after further revision, in an special issue of a Journal (approval pending).

Submission Instructions
===================================

All papers need to be submitted electronically in PDF format. Submitted papers must not substantially overlap with papers that have been published or that are simultaneously submitted to a journal or a conference with proceedings. Papers must be clearly presented in English, must not exceed 6-8 pages (short paper) or 12-14 pages (regular paper) in Springer LNCS format, including tables, figures, references and appendixes. Submission of a paper should be regarded as a commitment that, should the paper be accepted, at least one of the authors will register and attend the conference to present the work. All works submitted to the workshop will be reviewed by at least three experts of the UCER Program Committee. Upon the evaluation of the referees, the Program Committee will select papers to be included in the workshop agenda. The workshop's proceedings will be published by Springer in the Lecture Notes for Computer Science Series. See LNCS web page for more info.

Submissions site EasyChair.


Important Dates
===================================
Paper Submission Deadline: July 17th, 2016 (Last Extension) Acceptation Notification: September 15th, 2016 Camera-Ready Submission: October 15th, 2016 Workshop at ICA3PP 2016: December 14-16, 2016

Contact
===================================
Please email inquiries concerning the workshop to Dr. Juan Durillo (juan@dps.uibk.ac.at), Dr. Fabrizio Marozzo (Fabrizio Marozzo fmarozzo@dimes.unical.it), and Prof. Pedro Alonso (palonso@upv.es).

----------------------------------------------------------------------------------------------------------------------

--
Fabrizio Marozzo, PhD
DIMES - University of Calabria, Italy


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HIPEAC Conference 2017: Call for Workshops/Tutorials - SUBMISSION DEADLINE EXTENDED TO JULY 1st, 2016

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Call for Workshop/Tutorial ProposalsSubmission Deadline Extension: July 1st, 2016
The success of the workshops and tutorials of the previous years’ HiPEAC Conferences in Amsterdam and Prague with more than 35 events each encouraged the HiPEAC 2017 organizers to try following this success story again. Hence, in conjunction with the 12th HiPEAC Conference in Stockholm, Sweden, January 23-25, 2017 (see http://www.hipeac.net/conference), we will organize parallel workshops and tutorials. Proposals for workshops and tutorials covering at least one of the following topics are welcome:
·         High performance computer architecture: processor architecture, multi-/many-core system design, reconfigurable architectures.
·         Software development for high performance parallel systems: development patterns/automatic techniques for parallel and reconfigurable architectures.
·         Tools for compilation, evaluation, optimization as well as synthesis of high performance parallel systems: compiler support, tracing, and debugging for parallel and reconfigurable architectures, high-level synthesis.
·         Embedded (parallel) computer architectures: embedded homogeneous and heterogeneous multicore architectures, embedded reconfigurable architectures, embedded real-time systems, mixed criticality system support, dependable systems.
·         Software support for embedded architectures: tracing and real-time analysis of embedded applications, runtime software.
·         (Real-Time) Operating and runtime systems for embedded parallel computer architectures.
·         Crazy architectural ideas: any idea to solve computational problems away from the conventional concepts.
·         Low-Power Solutions: Software, Runtime, Compilation, Hardware, Error-Aware Computation, Sub-Threshold operation, Approximate Computing, Reversible Computing.
·         Future Scalable Memory Architectures: Processing-In-Memory, Near-Memory Computing, Intelligent Memory, etc.
·         Green Data Centers / Microserver: System architecture, Software tools.
·         Cloud, Fog, and Edge Computing: Architectures, Systems, Tools, Evaluation, Applications, Benchmarking.
We also appreciate industrial and EC project based workshops that fit into one of the mentioned focuses.
A workshop proposal should contain the following items:
·         Title of the workshop (including abbreviation)
·         Organizers and their affiliations
·         Main topics
·         Preliminary deadlines
·         Expected duration and format of the workshop (half or full day, keynote, talks, panel)
·         Expected number of talks and attendance and, if the workshop took place before, location and time
·         Please indicate if you plan to publish an open CFP or if you plan to have invited talks only.
For a tutorial proposal please include the following information:
·         Title of the tutorial
·         Organizers and presenters with affiliations and a short biography
·         Abstract of the tutorial and a list of the covered topics
·         Some related bibliography
·         Expected duration and format (half or full day, talk with demo or talk only)
·         Expected attendance and, if the tutorial was held before, location and time
If the proposed event is sponsored by a third party (e.g. industry), please indicate that in the proposal.
Please submit a one page PDF with your proposal by email to the workshop and tutorial chairs
Diana Goehringer (
diana.goehringer@rub.de) and Pedro Trancoso (pedro@cs.ucy.ac.cy)
not later than July 1st, 2016.




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Wednesday 22 June 2016

CCPE's Special Issue on Trends in High-Performance Interconnection Networks - Deadline extended to July 21

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*** Deadline extended: July 21

======================================================================== 

      Special Issue on Trends in High-Performance Interconnection Networks
                  in the Exascale and Big-Data Era

                  Wiley Journal of Concurrency and 
                Computation: Practice and Experience  


========================================================================

GUEST EDITORS

  * Pedro Javier Garcia, University of Castilla-La Mancha, Spain
  * Jesus Escudero-Sahuquillo, University of Castilla-La Mancha, Spain

SCOPE

By the year 2023, High-Performance Computing (HPC) Systems are expected to break the 
performance barrier of the Exaflop (10^18 FLOPS) while their power consumption is kept at
current levels (or incremented marginally), what is known as the Exascale challenge. 
In addition, more storage capacity and data-access speed is demanded to HPC clusters and
datacenters to manage and store huge amounts of data produced by software applications,
what is known as the Big-Data challenge. Indeed, both the Exascale and Big-Data 
challenges are driving the technological revolution of this decade, motivating big research
and development efforts from industry and academia. In this context, the interconnection 
network plays an essential role in the architecture of HPC systems and datacenters, as the
number of processing or storage nodes to be interconnected in these systems is very likely
to grow significantly to meet the higher computing and storage demands. Besides, the 
capacity of the network links is expected to grow, as the roadmaps of several interconnect
standards forecast. Therefore, the interconnection network should provide a high 
communication bandwidth and low latency, otherwise the network will become the bottleneck
of the entire system. In that regard, many design aspects are considered when it comes to
improve the interconnection network performance, such as topology, routing algorithm, 
power consumption, reliability and fault tolerance, congestion control, programming models,
control software, etc.

All researchers and professionals, both from industry and academia, working in the area of
interconnection networks for scalable HPC systems and Datacenters, and especially those 
involved in Exascale performance and Big-Data, are encouraged to submit a paper to this 
special issue.

TOPICS OF INTEREST

The list of topics covered by this Special Issue includes, but is not limited to, the 
following:

* Interconnect architectures and network technologies for high-speed, low-latency interconnects.
* Scalable network topologies, suitable for interconnecting a huge number of nodes.
* Power saving policies in the interconnect devices and network infrastructure, both at software and hardware level.
* Emerging ideas, work-in-progress and early, high-impact achievements.
* Good practices in the configuration of the network control software.
* Network communication protocols: MPI, RDMA, Hadoop, etc.
* APIs and support for programming models.
* Routing algorithms.
* Quality of Service (QoS).
* Reliability and Fault tolerance.
* Load balancing and traffic scheduling.
* Network Virtualization.
* Congestion Management.
* Applications and Traffic characterization.
* Modeling and simulation tools.
* Performance Evaluation.

Note that papers focused on topics that are too far from the design, development and 
configuration of high-performance interconnects for HPC systems and Datacenters 
(e.g., mobile networks, intrusion detection, peer-to-peer networks or grid/cloud computing)
will be automatically considered as out of scope and rejected without review.

IMPORTANT DATES

Deadline for submissions:    June 30, 2016 (extended to July 21)
First rounds of review:      September 7, 2016
Deadline for revised papers: October 7, 2016
Final decision notification: October 23, 2016
Camera Ready:                October 30, 2016
Estimated publication date:  January 31, 2017

All deadlines are set at 11:59 p.m. anywhere on Earth

INSTRUCTIONS FOR AUTHORS

* This call is open for all contributions, but it also invites selected papers from the 
  2nd edition of the HiPINEB workshop (http://hipineb.i3a.info/hipineb2016).

* Authors must abide by the requirement of adding significant novelty to the papers 
  submitted to this special issue. Extended versions of conference papers must contain at
  least 50% new content. Besides, it is mandatory to attach a cover letter to any 
  submission, explaining the main contributions of the paper. 
  
* Manuscripts should not exceed 25 pages in length.
  
* It is expected that submissions will align with the topics of interest listed above.
  
* Manuscripts should accomplish the general rules defined at:

* Papers should be submitted via Manuscript Central to special issue “HiPINEB2016”:

ADDITIONAL INFORMATION

For more information about this special issue or if you have any question, please contact


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