Thursday 27 October 2016

EuroMPI/USA 2017 Call for Workshops

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EUROMPI/USA 2017 CALL FOR WORKSHOPS

Experts in parallel and high-performance computing areas related to or
benefiting from MPI are invited to share their expertise with the
broader MPI community by submitting proposals for workshops to be
co-located with the EuroMPI/USA 2017 conference that will be held on
September 25-28, 2017 in Chicago, Illinois. The EuroMPI/USA 2017
workshop program will provide an opportunity for researchers to
present preliminary, new work and work that can complement and extend
the topics covered by EuroMPI/USA 2017 and, thus, will give attendees
access to the latest work in progress in the fields. EuroMPI/USA 2017
invites proposals for workshops on the broadest possible range of
topics related to, complementing or challenging the message-passing
paradigm in general and MPI in particular. The EuroMPI/USA workshops
will all take place on September 25, 2017.

TOPIC CATEGORIES

Workshops on all areas with a relation to MPI, its usage or
implementation, or complementary or challenging to the MPI paradigm
are invited. Workshops can also be fora to present new work in an
early stage. Possible topics include but are not limited to the
following:

- Use of MPI in new and unconventional applications
- Paradigms and application areas that challenge the message-passing
  model
- New message-passing models
- Different high-performance programming models and interfaces like
  PGAS, streaming models, etc.
- Irregular and non-numerical applications on large-scale systems
- New applications areas
- Use of accelerators in applications and programming interfaces
- Large-scale scientific simulation

Workshop contributions can be included in the ACM conference
proceedings.

SUBMISSION GUIDELINES

Proposals are limited to an up to 3 page description that should
include the following:

- A title, an abstract (400 words maximum), and a syllabus;
- Discussion of the topic's relevance, suitability to EuroMPI/USA,
and workshop goals;
- A description of the target audience;
- An indication of half-day or full-day duration;
- If applicable, details on previous instantiations of the workshop,
including attendance numbers.

In addition to the 3 page description, please include the following:

- A brief biographical sketch of each workshop organizer (at most 1
  page
per organizer).

Workshop proposals will be evaluated as they are received. Decisions
will be made based on the proposal content and its relationship to any
other workshop proposals that have been accepted or received at the
time the proposal is received. Since this policy may result in the
workshop program being completed early, EuroMPI/USA 2017 reserves the
right to close workshop submissions prior to the date listed below.

A single pdf file with all the material described above should be
submitted to the Euro MPI/US 2017 online submission
system at https://easychair.org/conferences/?conf=eurompiusa2017
under the workshop track.

Workshops should suggest their own submission deadlines, but the
camera-ready deadline for accepted contributions should follow the
camera-ready deadline for the main conference, in order to guarantee
inclusion of workshop papers in the ACM proceedings.  Workshop
organizers will themselves be responsible for managing submission and
review process.

The length of a workshop will be determined based on the following
policy:

- Workshops that accept ten or more papers will be provided space
for a full day program;
- Workshops that accept seven to nine papers will be provided space
for four and a half hours (not including breaks);
- Workshops that accept five or six papers will be provided space
for three hours (not including breaks);
- Workshops that accept three or four papers will be provided space
for a half hour per paper;
- Workshops with fewer accepted papers will be canceled.

EuroMPI/USA 2017 will consider increasing the time allocated to a
workshop
if space is available.

EuroMPI/USA 2017 will provide free conference registration for one
keynote speaker to workshops that accept ten or more papers. The free
registration cannot be used by a workshop organizer, even if the
organizer presents a keynote.

IMPORTANT DATES

* Workshop proposal submission cut-off deadline: January 15, 2017
* Camera-ready workshop papers deadline: August 18, 2017

EUROMPI/USA 2017 WORKSHOPS CHAIR

Jesper Larsson Träff, Vienna University of Technology

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CFP: WP3 First Workshop on Pioneering Processor Paradigms in conjunction with HPCA'17

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=====================================================
Call for Contributions - WP3 - 2016
FIRST WORKSHOP ON PIONEERING PROCESSOR PARADIGMS (WP3)
in conjunction with the 23rd IEEE Symposium on High
Performance Computer Architecture (HPCA'16)
4 February, 2017 / Austin, TX, USA
http://wp3workshop.website/
=====================================================

Innovations in instruction set architecture (ISA),
processor microarchitecture and supportive advances in
circuit design, compilers, semiconductor technology,
pre-silicon specification, modeling and validation
have all been essential elements of the computer
systems revolution that has transformed human society
so dramatically over the last six decades or more.
In the late CMOS era, with power and reliability walls
already causing major paradigm shifts, the need for
new innovations in cross-layer, hardware-software
design and modeling are being called for to help
keep the IT industry moving and growing at historical
rates.

In trying to forge a path of innovation, it is sometimes
worth examining the past to look for major paradigm
shifts in (micro)-architecture, circuits, modeling
and software that helped us keep going in the face
of past technology-driven disruption points. With
this in mind, we present a new workshop pioneering
processor paradigms (P3). With the help of true
pioneers as well as budding new researchers, P3 will
take a retrospective look at how past technological
hurdles were circumvented through major innovations.
The goal is to learn from the past in devising new
solution strategies for the future.

The P3 workshop will offer a number of invited talks
from true pioneers as well as reviewed selections
from the new generation of researchers and teachers
who are eager to take a retrospective look into
surveying past pioneering work that can teach us a
lesson about solution strategies of the future.

*** Important Dates:

- Submission deadline: November 27, 2016
- Notification of acceptance: December 11, 2016
- Final paper submission: January 8, 2017
- Workshop date: February 4, 2017

** Call for contributions

The workshop on pioneering processor paradigms invites
survey (or tutorial)-like submissions for review. The
ideal paper would highlight a single pioneering paper
(or set of papers) constituting a major processing,
design, modeling or software paradigm shift in the past.
In addition to explaining the context and basic concepts
articulated in such work, the author(s) should draw
relevant conclusions about how this pioneering work
could or should influence computing paradigms of the
future.

Note: Ph.D dissertation research topic proposals from
(junior graduate students) that contain a survey of a
key paper or two to build up the motivational justification
of the proposal are quite welcome, for example.

** Topics of interestest

Example topic areas include (but are not limited to):

- Processing and cache taxonomy papers.
- RISC architectures and CISC-to-RISC dynamic translation
  support.
- Processor pipelining, super scalar processing and
  branch prediction innovations.
- Register renaming, out-of-order execution and precise
  interruption.
- Cycle-accurate processor performance modeling.
- Innovations in floating point arithmetic units and
  vector/SIMD acceleration.
- VLIW architectures.
- Multi-threading, multiscalar and speculative multi-threading.
- Homogeneous and heterogeneous multi-core processors;
  accelerator-enabled efficiency boost.
- Power, temperature, and reliability-aware computing –
  with associated modeling innovations.
- Compiler innovations in support of novel microarchitectural
  paradigms.
- Circuit design innovations in support of (micro)-architectural
  paradigm shifts.

*** Registration
Refer to main conference: http://hpca2017.org/

*** Hotel Reservation
Refer to main conference: http://hpca2017.org/

For more details, please see http://wp3workshop.website/
====================================================

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GPGPU 2017 CFP

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GPGPU 2017 Workshop CFP
======================

The goal of this workshop is to provide a forum to discuss new and emerging general-purpose programming architectures, environments and platforms, as well as evaluate applications that have been able to harness the horsepower provided by these platforms. This year's work is particularly interested in new heterogeneous architecture/platforms, new forms of concurrency, and novel/irregular applications that can leverage these platforms. Papers are being sought on many aspects of GPUs, including (but not limited to):
>> GPU Applications
>> GPU Programming Environments
>> GPU Runtime Systems
>> GPU Complication
>> GPU Architectures
>> Multi-GPU Systems
>> GPU Power/efficiency
>> GPU Reliability
>> GPU Benchmarking/measurements
>> Heterogeneous Architectures/platforms

Important Dates:

>> Papers due: November 20, 2016
>> Notification: December 20, 2016
>> Final Paper Due: January 15, 2017

For more details, please refer to: http://gpgpu10.athoura.com/index.html


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Tuesday 25 October 2016

MULTIPROG-2017: Deadline Extension (new deadline is November 4th)

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*** NOTE: DEADLINE EXTENDED TO NOVEMBER 4TH! ***


CALL FOR PAPERS
---------------

The Tenth International Workshop on 
Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2017)

To be held in conjunction with: 
the 12th International Conference on 
High-Performance and Embedded Architectures and Compilers (HiPEAC) 
Stockholm, Sweden, January 24, 2017


Goal of the Workshop
--------------------

Computer manufacturers have embarked on the many-core roadmap, promising to add 
more and more cores/hardware threads on their chips. The ever-increasing number 
of cores and heterogeneity in architectures has placed new burdens on the 
programming community. Software needs to be parallelized and optimized for 
accelerators such as GPUs in order to take advantage of the new breed of 
multi-/many-core computers. As a result, progress in how to easily harness the 
computing power of multi-core architectures is in great demand.

The tenth edition of the MULTIPROG workshop aims to bring together researchers 
interested in programming models, runtimes, and computer architecture. The 
workshop's emphasis is on heterogeneous architectures and covers issues such as: 

    * How can future parallel programming models improve software productivity?
    
    * How should compilers, runtimes and architectures support programming 
      models and emerging applications?
    
    * How to design efficient data structures and innovative algorithms?

MULTIPROG is intended for quick publication of early results, work-in-progress, 
etc., and is not intended to prevent later publication of extended papers. 
Informal proceedings with accepted papers will be made available at the workshop 
and online at the workshop’s web page http://research.ac.upc.edu/multiprog/.


Topics of interest
------------------
Papers are sought on topics including, but not limited to:
    * Multi-core architectures
        o Architectural support for compilers/programming models
        o Processor (core) architecture and accelerators, in particular GPUs
        o Memory system architecture
        o Performance, power, temperature, and reliability issues
    * Heterogeneous computing
        o Algorithms and data structures for heterogeneous systems
        o Applications for heterogeneous computing and real-time graphics
    * Programming models for multi-core architectures
        o Language extensions
        o Run-time systems
        o Compiler optimizations and techniques
    * Benchmarking of multi-/many-core architectures
        o Tools for discovering and understanding parallelism
        o Tools for understanding performance and debugging
        o Case studies and performance evaluation


Important dates
---------------
Paper submission: November 4, 2016
Author notification: November 27, 2016


Paper submission
----------------
MULTIPROG accepts contributions of regular research papers and short position
papers describing early research on emerging topics. When preparing your
submission please adhere to the following format specification:

* Regular research papers:

Regular research papers should preferably use LNCS format (up to 12 pages, not
including references). Single column (up to 12-Pages) or double column (up to
6-pages) formats are also accepted.  

* Short position papers:

Short position papers should preferably use LNCS format (4-6 pages, not
including references). Single column (4-6 pages) or double column (2-3 pages)
formats are also accepted. Papers in this category should explicitly indicate
"Position Paper:" in front of the title of their manuscript.  

The authors of the accepted papers will be requested to provide the final
version of their paper in LNCS format. Please use the templates below:




Organizers
----------
Miquel Pericàs            Chalmers         Sweden   miquelp[at]chalmers.se
Vassilis Papaefstathiou   FORTH-ICS        Greece   vaspap[at]chalmers.se 
Oscar Palomar             U. Manchester    UK       oscar.palomar[at]manchester.ac.uk
Ferad Zyulkyarov          BSC              Spain    ferad.zyulkyarov[at]bsc.es


Program committee
------------------
Abdelhalim Amer         Argonne National Lab            USA
Ali Jannesari           UC Berkeley                     USA
Avi Mendelson           Technion                        Israel
Chris Adeyeni-Jones     ARM                             UK
Christos Kotselidis     University of Manchester        UK
Dong Ping Zhang         AMD                             USA
HÃ¥kan Grahn             Blekinge TH                     Sweden
Hans Vandierendonck     Queen’s University Belfast      UK
Kenjiro Taura           University of Tokyo             Japan
Magnus Själander        NTNU                            Norway
Oscar Plata             University of Malaga            Spain
Pedro Trancoso          University of Cyprus            Cyprus
Polyvios Pratikakis     FORTH-ICS                       Greece
Roberto Gioiosa         PNNL                            USA
Sasa Tomic              IBM Research                    Switzerland
Timothy G. Mattson      Intel                           USA
Trevor E. Carlson       Uppsala University              Sweden
Yungang Bao             ICT-CAS                         China


Workshop site
-----------------

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CfP for the HIPS 2017 workshop

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== CFP for the HIPS 2017 Workshop at the IPDPS Conference ==

The 22nd International workshop on High-level Parallel Programming Models and
Supportive Environments (HIPS, http://inside.mines.edu/~bwu/sites/HIPS2017/)
will take place on Monday, 2017-05-29 in conjunction with the IPDPS conference
(http://www.ipdps.org/ipdps2017/) in Orlando, Florida, USA.

We kindly invite you to send your submissions to HIPS 2017. HIPS focuses on
high-level programming of multiprocessors, compute clusters, and massively
parallel machines. Like previous workshops in the HIPS series since 1996, this
event serves as a forum for research in the areas of parallel applications,
language design, compilers, runtime systems, and programming tools. It
provides a timely and lightweight forum for scientists and engineers to
present the latest ideas and findings in these rapidly changing fields.

The workshop topics include but are not limited to:

* New programming languages and constructs for exploiting parallelism and
locality
* Experience with and improvements for existing parallel languages and run-
time environments such as MPI, OpenMP, Cilk, UPC, Co-array Fortran, X10,
Chapel, Charm++, and OpenCL
* Parallel compilers, programming tools, and environments
* (Scalable) tools for performance analysis, modeling, monitoring, and
debugging
* OS and architectural support for parallel programming and debugging
* Software and system support for extreme scalability including fault
tolerance
* Programming environments for heterogeneous multi-core systems and
accelerators such as GPUs, FPGAs, and MICs
* Domain specific languages exploring embedded and stand-alone languages,
libraries and runtime for focused application areas
* Languages and runtime support for multi-science/coupled codes, including but
not limited to ensemble computing and UQ


== Paper Submission ==

Please submit novel papers with up to 10 pages in IEEE style via EasyChair at
https://easychair.org/conferences/?conf=hips2017. Deadlines are:

* Submissions due: **2017-01-29**
* Author notification: **2017-02-27**
* Camera-ready papers due: **2017-03-10**

For details and paper templates see the workshop webpage at http://
inside.mines.edu/~bwu/sites/HIPS2017/#submission-deadlines.


== Organizers ==

HIPS 2017 is organized by Bo Wu (Colorado School of Mines, Golden, CO USA) and
Andreas Knüpfer (Technische Universität Dresden, Dresden, Germany)

Please see http://inside.mines.edu/~bwu/sites/HIPS2017/#committees for the
HIPS Steering Committee and the Program Committee as well as the HIPS workshop
history.


We are looking forward to see you there!
Bo and Andreas


--
Dr. rer. nat. Andreas Knüpfer
Deputy Director/CTO
Technische Universität Dresden
Center for Information Services and HPC (ZIH)
Willersbau A113, Zellescher Weg 12, 01062 Dresden
Tel. +49 351 463 38323
Fax. +49 351 463 37773
Email: andreas.knuepfer@tu-dresden.de
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Saturday 15 October 2016

CFP: Second International Conference on Data Mining & Knowledge Management (DaKM 2017)

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Second International Conference on Data Mining & Knowledge Management (DaKM 2017)

January 2~3, 2017, Zurich, Switzerland.
Call for Papers
The Second International Conference on Data Mining & Knowledge Management (DaKM 2017) provides a forum for researchers who address this issue and to present their work in a peer-reviewed forum. Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to these topics only
Topics of Interest Include, but are not limited to:
Data Mining Foundations
Parallel and Distributed Data Mining Algorithms, Data Streams Mining, Graph Mining, Spatial Data Mining, Text Video, Multimedia Data Mining, Web Mining, Pre-processing Techniques, Visualization, Security and Information Hiding in Data Mining.
Data Mining Applications
Databases, Bioinformatics, Biometrics, Image Analysis, Financial Modeling, Forecasting, Classification, Clustering, Social Networks, Educational Data Mining.
Knowledge Processing
Data and Knowledge Representation, Knowledge Discovery Framework and Process, Including Pre- and Post-processing, Integration of Data Warehousing, OLAP and Data Mining, Integrating Constraints and Knowledge in the KDD Process , Exploring Data Analysis, Inference of Causes, Prediction, Evaluating, Consolidating, and Explaining Discovered Knowledge, Statistical Techniques for Generation a Robust, Consistent Data Model, Interactive Data Exploration/visualization and Discovery, Languages and Interfaces for Data Mining, Mining Trends, Opportunities and Risks, Mining from Low-Quality Information Sources.
Paper Submission
Authors are invited to submit papers through the Conference Submission System by October 23, 2016. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by Computer Science Conference Proceedings in Computer Science & Information Technology (CS & IT) series (Confirmed)..
Selected papers from DaKM 2017, after further revisions, will be published in the special issue of the following journals
International Journal of Database Management Systems ( IJDMS )
International Journal of Data Mining & Knowledge Management Process ( IJDKP )
Important Dates

Submission Deadline : October 23, 2016
Authors Notification : November 20, 2016
Final Manuscript Due : November 30, 2016


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IPDPS Call for paper: deadline Oct 18

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---------------------------------------
IPDPS 2017 Call For Papers
---------------------------------------

October 11, 2016 release
31st IEEE International Parallel & Distributed Processing Symposium
May 29 – June 2, 2017
Orlando, Florida USA

This is the short version of the CfP. See the full version at
http://www.ipdps.org/ipdps2017/2017_call_for_papers.html

... Abstracts due October 18, 2016 AOE
... Submissions due October 23, 2016 AOE

*** SCOPE ***
Authors are invited to submit manuscripts that present original
unpublished research in all areas of parallel and distributed
processing, including the development of experimental or commercial
systems. Work focusing on emerging technologies and interdisciplinary
work covering multiple IPDPS areas are especially welcome.

Topics of interest include, but are not limited to:
* Parallel and distributed algorithms;
* Applications of parallel and distributed computing;
* Parallel and distributed architectures;
* Parallel and distributed software.

Papers that cross the boundaries of the four traditional tracks of
IPDPS (Algorithms, Applications, Architecture and Software) are
encouraged and can be submitted to a newly established
multidisciplinary track. During submission of multidisciplinary
papers, authors should indicate their subject areas that can come from
any track.

*** BEST PAPERS AWARDS ***

The program committee will nominate papers for recognition in several
categories including the four conference topic areas as well as best
multidisciplinary paper and will consider other paper attributes that
merit recognition from the conference. The five top best papers will
be selected for presentation and the others will receive honorable
mention in the conference program.

*** WHAT/WHERE TO SUBMIT ***

Abstracts must be submitted by October 18th; submitted abstracts may
not exceed 500 words. Manuscripts must be submitted by October 23rd;
submitted manuscripts may not exceed ten (10) single-spaced
double-column pages using 10-point size font on 8.5x11 inch pages
(IEEE conference style), including figures, tables, and references.
The submitted manuscripts should include author names and
affiliations. Style templates are available on
http://www.ipdps.org/ipdps2017/2017_call_for_papers.html

Files should be submitted by following the instructions at the
EasyChair portal available at
https://easychair.org/conferences/?conf=ipdps17.

*** REVIEW OF MANUSCRIPTS ***

All submitted manuscripts will be reviewed. Submissions will be judged
on correctness, originality, technical strength, significance,
potential impact, quality of presentation, and interest and relevance
to the conference scope. Submitted papers should NOT have appeared in
or be under consideration for another conference, workshop or journal.
There will be a one week review feedback and author response period
from November 28th to December 5th. Questions may be sent to
PC2017@ipdps.org.

*** IMPORTANT DATES ***

- October 18, 2016:  Registration of papers with abstracts will be
accepted up to end of day ANYWHERE ON EARTH.
- October 23, 2016: Submission of registered papers will be accepted
up to end of day ANYWHERE ON EARTH.
- Review feedback to authors….…November 28, 2016
- Author response to feedback…..December 5, 2016
- Author notification.......January 8, 2017
- Camera-ready due.....February 15, 2017

*** PROGRAM/ORGANIZER COMMETTEES ***
GENERAL CHAIR
Michela Taufer (University of Delaware, USA)

PROGRAM CHAIR
Marc Snir (University of Illinois at Urbana Champaign, USA)

PROGRAM VICE-CHAIRS:
ALGORITHMS:
Pierre Fraigniaud (IRIF, France)
APPLICATIONS:
Robert D. Moser (UT Austin, USA) &
George Biros (University of Texas, Austin, USA)
ARCHITECTURE:
Hillery Hunter (IBM Research, USA) &
Robert Senger (IBM Research, USA)
SOFTWARE:
Pavan Balaji (Argonne National Laboratory, USA) &
Sunita Chandrasekaran (University of Delaware, USA)
MULTIDISCIPLINARY:
Torsten Hoefler (ETH Zurich, Switzerland)

----------------------------------------------------------------------------
...Follow us on Facebook at https://www.facebook.com/IPDPS
...Follow us on Twitter at  https://twitter.com/IPDPS
...Follow us on Linkedin at https://www.linkedin.com/groups/8550095
-----------------------------------------------------------------------------
Sponsored by IEEE Computer Society Technical Committee on Parallel Processing
In cooperation with ACM SIGARCH, ACM SIGHPC, IEEE Computer Society
Technical Committee on Computer Architecture, and IEEE Computer
Society Technical Committee on Distributed Processing
-----------------------------------------------------------------------------
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Wednesday 12 October 2016

CFP: BigGraphs 2016 workshop at IEEE BigData 2016

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The Third International Workshop on High Performance
Big Graph Data Management, Analysis, and Mining (BigGraphs 2016)

To be held in conjunction with IEEE BigData 2016
Dec 5-8, 2016, Washington, D.C., USA.

Website:
  http://www.biggraphs.org

Important Dates:
  Oct 20, 2016: Submission deadline
  Nov  6, 2016: Notification of paper acceptance to authors
  Nov 15, 2016: Camera-ready submissions due

Call for papers:
Modern Big Data increasingly appears in the form of complex graphs and networks.
Examples include the physical Internet, the world wide web, online social networks,
phone networks, and biological networks. In addition to their massive sizes, these
graphs are dynamic, noisy, and sometimes transient. They also conform to all five Vs
(Volume, Velocity, Variety, Value and Veracity) that define Big Data. However, many
graph-related problems are computationally difficult, and thus big graph data brings
unique challenges, as well as numerous opportunities for researchers, to solve various
problems that are significant to our communities. This workshop aims to bring together
researchers from different paradigms solving big graph problems under a unified
platform for sharing their work and exchanging ideas. We are soliciting novel and
original research contributions related to big graph data management, analysis, and
mining (algorithms, software systems, applications, best practices, performance).
Significant work-in-progress papers are also encouraged. Papers can be from any of
the following areas, including but not limited to:
* Parallel algorithms for big graph analysis on HPC systems
* Heterogeneous CPU-GPU solutions to solve big graph problems
* Extreme-scale computing for large graph, tensor, and network problems
* Sampling and summarization of large graphs
* Graph algorithms for large-scale scientific computing problems
* Graph clustering, partitioning, and classification methods
* Scalable graph topology measurement: diameter approximation,
  eigenvalues, triangle and graphlet counting
* Parallel algorithms for computing graph kernels
* Inference on large graph data
* Graph evolution and dynamic graph models
* Graph streams
* Graph databases, novel querying and indexing strategies for RDF data
* Novel applications of big graph problems in bioinformatics, health care,
  security, and social networks
* New software systems and runtime systems for big graph data mining

Submissions must be at most 8 pages long, including all figures, tables, and references.
They must be formatted according to the style files used by the IEEE BigData 2016
conference proceedings. Papers must be submitted online through the workshop submissions
page (http://wi-lab.com/cyberchair/2016/bigdata16/scripts/submit.php?subarea=S19)
by 11.59 pm PDT (Pacific Daylight Time) on October 20, 2016.


Workshop Organizers:

  Nesreen Ahmed
  Intel Labs
  nesreen.k.ahmed@intel.com

  Mohammad Al Hasan
  Indiana University-Purdue University Indianapolis
  alhasan@cs.iupui.edu

  Kamesh Madduri
  The Pennsylvania State University
  madduri@cse.psu.edu

Program Committee:
 
Nesreen Ahmed (Intel Labs)
  Mohammad Al Hasan (Indiana University - Purdue University)
  Ariful Azad (Lawrence Berkeley National Laboratory)
  Sanjukta Bhowmick (University of Nebraska at Omaha)
  Mehmet Deveci (Sandia National Laboratories)
  Nick Duffield (Texas A&M University)
  Assefaw Gebremedhin (Washington State University)
  Oded Green (Georgia Institute of Technology)
  Irena Holubova (Charles University)
  Kamesh Madduri (The Pennsylvania State University)
  Ali Pinar (Sandia National Laboratories)
  Ryan Rossi (Palo Alto Research Center)
  George Slota (Rensselaer Polytechnic Institute)
  Narayanan Sundaram (Intel Labs)
  Ted Willke (Intel Labs)
  Yinglong Xia (Huawei Research America)
 

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IEEE NetSoft 2017 Call for Submissions


Monday 10 October 2016

Deadline extended to Oct 17, 2016 for WACEBI 2016 workshop

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2016 Workshop on Accelerator-Enabled Algorithms and Applications in Bioinformatics (WACEBI 2016)
in conjunction with IEEE BIBM 2016, Shenzhen, China, December 15-18, 2016

Deadline extended to Oct. 17, 2016 (hard deadline).

Call for Papers:
Advances in high-throughput technologies (such as cost-affordable sequencing of whole genomes, population-scale variation screening, or mass spectrometry-based proteomics) are continually propelling related bioinformatics research into the era of big data. This establishes a strong need of sophisticated parallel algorithms and architectures for fast and efficient processing of large-scale biological datasets. To address these challenges, diverse accelerators have been used to accelerate important and computationally demanding applications in Bioinformatics. Typical accelerators include but not limited to FPGAs, GPUs, Intel Xeon Phi coprocessors, Intel SSE and AVX vector processing units, Micron Automata Processors, and custom hardware chips. Meanwhile, various parallel algorithms inherently enabling to use accelerators have been or are being developed as well.

This workshop focuses on accelerator-enabled parallel algorithms and applications in Bioinformatics, and will award a Best GPU Paper/Talk Award to an outstanding paper based on GPU computing. This Best GPU Paper/Talk Award is generously sponsored by NVIDIA Corporation and the prize is one GeForce GTX Titan X graphics card (state-of-the-art GPU and worth of $1000). We will consider original submissions that (1) use accelerator technologies to address important biological problems, or (2) propose new parallel algorithms and software tools elaborated to have the potential and feasibility to exploit accelerators. Topics of interest include but are not limited to:
  (1) Biological sequence database
  (2) Biological sequence analysis
  (3) Computational genomics and proteomics
  (4) Infrastructure and systems tools for high-performance bioinformatics
  (5) Metagenomics
  (6) Next-generation sequencing
  (7) Phylogeny inference
  (8) Protein structure prediction and modeling
  (9) Workflow and systems for big biological data management

The WACEBI 2016 workshop will be held in conjunction with the IEEE International Conference on Bioinformatics and Biomedicine 2016 (IEEE BIBM 2016), Shenzhen, China, Dec. 15-18, 2016. Please visit the workshop at http://www.cc.gatech.edu/~yliu/wacebi2016

Online Submission
Please submit your papers (up to 8 pages IEEE 2-column format) through the online submission system (https://wi-lab.com/cyberchair/2016/bibm16/scripts/submit.php?subarea=S09&undisplay_detail=1&wh=/cyberchair/2016/bibm16/scripts/ws_submit.php). You can download the format instruction from http://www.ieee.org/conferences_events/conferences/publishing/templates.html). Electronic submissions (in PDF or Postscript format) are required. Accepted papers by this workshop will be published by the IEEE Computer Society. Additionally, we plan to publish selected papers (with technically significant expansion and revision) as a special issue in some highly respected journal. In addition, if you would like to give an invited talk in this workshop, please submit a one-page abstract paper for consideration.

Important Dates
August 23, 2016: Paper submission open
Extened to Oct. 17, 2016 (hard deadline): Due date for full workshop papers submission
November 10, 2016: Notification of paper acceptance to authors
November 20, 2016: Camera-ready of accepted papers
December 15, 2016: Workshop

Program Chairs
Yongchao Liu (Georgia Institute of Technology, USA)
Bertil Schmidt (University of Mainz, Germany)

Program Committee Members
Sunita Chandrasekaran (University of Delaware, USA)
Scott Emrich (University of Notre Dame, USA)
Jorge Gonzalez-Dominguez (University of A Coruna, Spain)
Andreas Hildebrandt (University of Mainz, Germany)
Ananth Kalyanaraman (Washington State University, USA)
Ben Langmead (Johns Hopkins University, USA)
Dominique Lavenier (INRIA/IRISA, France)
Tao Li (Nankai University, China)
Weiguo Liu (Shandong University, China)
Ruibang Luo (Johns Hopkins University, USA)
Jan Schroeder (Walter and Eliza Hall Institute of Medical Research, Australia)
Sharma Thankachan (Georgia Institute of Technology, USA)
Gang Wang (Nankai University, China)
Jaroslaw Zola (The State University of New York at Buffalo, USA)

Contact
Yongchao Liu (yliu@cc.gatech.edu)
Bertil Schmidt (bertil.schmidt@uni-mainz.de)
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ISC 2017 CALL FOR WORKSHOPS

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######################################################################
## ISC 2017 CALL FOR WORKSHOPS 
######################################################################

Are you interested in hosting a workshop at the ISC High Performance conference? 

ISC is now accepting proposals for full- or half-day workshops. The goal of workshops is to provide attendees with a focused and in-depth platform for presentations, discussion and interaction in a particular subject area. We are inviting workshop proposals on topics related to all aspects of research, development, and application of large-scale, high-performance experimental and commercial systems. 

Topics include HPC computer architecture and hardware, programming models, system software, and applications, solutions for heterogeneity, reliability, and power efficiency of systems as well as how those areas apply to big data and cloud computing. 

Submitted workshop proposals will be reviewed by the ISC 2017 Workshops Committee, which is headed by Michela Taufer, University of Delaware (USA) and John Shalf, Lawrence Berkeley National Laboratory (USA).
Workshops will be held on Thursday, June 22 in the Marriott Frankfurt Hotel, the day after the ISC High Performance conference. Attendance will require a workshop pass. 

IMPORTANT DATES 

Pre-Submission Deadline(*)
Thursday, December 1, 2016, 11:59 pm AoE
 Pre-Submission NotificationThursday, December 15, 2016
 Final Submission DeadlineWednesday, February 15, 2017, 11:59 pm AoE
 Final NotificationWednesday, March 15, 2017
 WorkshopsThursday, June 22, 2017
 Final PDFs due for ProceedingsFriday, June 23, 2017
(*) The pre-submission deadline of December 1, 2016 is meant for workshops that want to disseminate their own call for papers and implement a peer-review process. Proposals for “regular” workshops without call for papers should be submitted by February 15, 2017.

SUBMISSION AND REVIEW PROCESS 

Workshop proposals can be submitted now via the ISC 2017 Linklings conference system at: 
https://ssl.linklings.net/conferences/isc_hpc/

Proposals need to be uploaded as a single PDF file. 

The Workshops Committee will peer review all workshop proposals submitted, select the workshops, and allocate their time slots. 

CONTACT AND FURTHER INFORMATION 

MS. HEIKE WALTHER <heike.walther@isc-group.com>

_________________________________________________

Michela Taufer
Associate Professor
Computer and Information Sciences
Biomedical Engineering
University of Delaware

Phone: (302) 831 0071
Fax: (302) 831 8458
E-Mail: taufer@acm.org
URL: http://www.cis.udel.edu/~taufer
GCLab: http://gcl.cis.udel.edu
D@H: http://docking.cis.udel.edu


Follow me on Twitter at: https://twitter.com/MichelaTaufer 
Follow my Group on Twitter at: https://twitter.com/TauferLab
__________________________________________________


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Sunday 9 October 2016

ISC HPC 2017: Call for Papers

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ISC 2017 CALL FOR RESEARCH PAPERS

The ISC research paper sessions provide first-class open forums for
engineers and scientists in academia, industry and government to
present and discuss issues, trends and results that will shape the
future of high performance computing.

Submitted research papers will be reviewed by the ISC 2017 Research
Papers Committee, which is headed by Dr. Pavan Balaji, Argonne
National Laboratory, with Prof. Dr. David Keyes, KAUST, as Deputy
Chair and Dr. Julian Kunkel, Deutsches Klimarechenzentrum, as
Proceedings Chair and Dr. Rio Yokota, Tokyo Institute of Technology,
as Proceedings Deputy Chair.

The ISC organizers as well as the German Gauss Center for
Supercomputing will again sponsor the call for research papers with
two awards for outstanding research papers: the Hans Meuer Award and
the GAUSS Award.

The research paper sessions will be held from Monday, June 19, through
Wednesday, June 21, 2017.  Attendance will require a Conference Pass.

IMPORTANT DATES

 * Full Submission Deadline: Friday, December 2, 2016, 11:59 pm AoE
 * Author Rebuttals: Monday, February 6 - Thursday, February 9, 2017
 * Notification of Acceptance: Monday, February 27, 2017
 * Camera-Ready Submission: Monday, March 27, 2017
 * Research Paper Sessions: Monday, June 19 - Wednesday, June 21, 2017
 * Final PDFs due for Proceedings: Friday, June 23, 2017

AREAS OF INTEREST

We encourage the submission of high-quality papers reporting original
work in theoretical, experimental and industrial research and
development. The ISC submission process will be divided into four
tracks this year for better manageability:

Architectures & Networks
 - Future design concepts of HPC systems
 - Multicore/manycore systems
 - Heterogeneous systems
 - Network technology
 - Domain-specific architectures
 - Memory technologies
 - Trends in the HPC chip market
 - Exascale Computing

Applications & Algorithms
 - Scalability on future architectures
 - Performance evaluation & tuning
 - Innovative domain-specific algorithms
 - Workflow management
 - Data analysis & visualization
 - Coupled simulations
 - Industrial simulations
 - Scalable Applications: 50k+

Data, Storage & Visualization
 - From big data to smart data
 - Memory systems for HPC & big data
 - File systems & tape libraries
 - Data intensive applications
 - Databases
 - Visual analytics
 - In-situ analytics

Programming Models & Systems Software
 - The art of parallel programming
 - Tools and Libraries for Performance and Productivity
 - Application of methods
 - Batch job management
 - Monitoring & administration tools
 - Production efficiency
 - Energy efficiency

Note: Submissions on other innovative aspects of high performance
computing are also welcome.

You will be asked to pick a primary and a secondary track for your
submission.

SUBMISSION & REVIEW PROCESS

 - Paper proposals need to be submitted via the ISC 2017 submission
   site at https://ssl.linklings.net/conferences/isc_hpc/ by Friday,
   December 2, 2016.

 - We only accept paper submissions which are formatted correctly in
   LNCS style (single column format) using either the LaTeX document
   class or Word template. For details on the author guidelines,
   please refer to Springer's website at
   http://www.springer.com/computer/lncs?SGWID=0-164-6-793341-0. Incorrectly
   formatted papers will be excluded from the reviewing process.

 - Paper submissions are required to be within 18 pages in the above
   mentioned LNCS style. This includes all figures and references.

 - Each paper will be peer-reviewed double-blind by at least 4
   reviewers and should be submitted in a form suitable for anonymous
   review. Papers will be evaluated by reviewers based on their
   novelty, fundamental insights and potential for long-term
   contribution.

 - Papers will go through a rebuttal phase to give authors the chance
   to respond to reviewer comments and to discuss them with the
   Research Papers Committee. During this phase, the reviews of your
   paper would be made available to you and you will have the
   opportunity to address any questions from the reviewers or aspects
   that you feel the reviewers might have misunderstood. The rebuttal
   would be in written format, and further instructions will be
   emailed to the authors. After the rebuttal period has closed, the
   Research Papers Committee members and chairs will have an
   opportunity to look through the author rebuttals and would be able
   to change their reviews based on this information. Final decisions
   will be made taking the reviews and rebuttals into consideration.

 - At an in-person Research Papers Committee meeting, each paper will
   be discussed before the acceptance decisions are made.


TERMS & CONDITIONS

 - By submitting a paper proposal, you agree to present the paper at
   ISC 2017 in Frankfurt, Germany.

 - Paper presenters need to be registered ISC 2017 participants. The
   ISC organizers will grant a 100% discount on the conference day
   pass to one presenter per paper for the day of their presentation
   (or an equivalent discount on the full conference pass).

 - Travel, accommodation, registration fees and other such costs will
   not be covered by the ISC organizers.


AWARDS

The following two awards will be given to outstanding research papers:

Hans Meuer Award

The Hans Meuer Award honors the most outstanding research paper
submitted to the conference's Research Papers Committee. This award
has been introduced in the memory of the late Dr. Hans Meuer, general
chair of the ISC conference from 1986 through 2014, and co-founder of
the TOP500 project.

From all submitted research papers, the Research Papers Committee will
select the overall best paper for the award. The winner will be
announced at the ISC High Performance Opening Session and will be
given the opportunity to present a keynote talk on their work in one
of the research paper sessions. The winner will also receive a cash
prize of 5,000 Euros, an award certificate, and a free conference pass
for ISC High Performance in 2017.

Gauss Award

The Gauss Award is sponsored by the German Gauss Center for
Supercomputing, which is a collaboration of the German national
supercomputing centers at Garching, Julich and Stuttgart.

The winner will receive a cash prize of 3,000 Euros, courtesy of the
Gauss Center, which will be presented by Professor Michael Resch,
chairman of the Gauss Award Committee, during the ISC Opening
Session. The award winner will also have the opportunity to present a
keynote talk on their paper during one of the research paper sessions.


PUBLICATION

The publication of the papers is managed by Proceedings Chair
Dr. Julian Kunkel with Dr. Rio Yokota, Tokyo Institute of Technology,
as Proceedings Deputy Chair.

All accepted research papers will be published in the Springer's
Lecture Notes in Computer Science (LNCS) series
(http://www.springer.com/lncs).  For the camera-ready version, authors
are automatically granted one extra page to incorporate reviewer
comments. The publication is free of charge. The papers can be
downloaded from Springer's website for a limited time after ISC
2017. The proceedings are indexed in the ISI Web of Science, EI
Engineering Index, ACM Digital Library, dblp, Google Scholar, IO-Port,
MathSciNet, Scopus, and Zentralblatt MATH.


SLIDE PROCEEDINGS

The ISC organizers will make the proceedings available online, with
presentation slides provided as PDF files, a week after the event. ISC
2017 attendees will receive an e-mail with the access link. Paper
authors are kindly requested to provide a PDF version of their
presentation slides to Ms. Heike Walther at
heike.walther@isc-group.com by Friday, June 23, 2017 at the latest.

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