CALL FOR PAPERS
6th Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools
(http://www.hipeac.net/rapido)
in Vienna, Austria, January, 2014
Held in conjunction with the 9th International Conference on High Performance Embedded Architectures and Compilers (HiPEAC) (http://www.hipeac.net/
==============================
Goal of the Workshop :
The focus of the RAPIDO?14 workshop is on methods and tools for rapid simulation and performance evaluation in embedded and high performance system design. Given continuous advances in chip technology, it is to be expected that future-generation processors will integrate numerous units on a single die, including multiple processor cores, multiple levels of (shared/private) caches or memories, and multiple dedicated accelerators, which will be glued together through a network on-chip (NoC).
The design space is huge though:
- How many cores do we need?
- Should we have a homogeneous or a heterogeneous design?
- When dynamic reconfiguration must be performed?
- How many caches/memories do we need?
- How to choose the instruction set(s) for these cores?
- What are the best code optimizations for a given application?
- How to combine the different metrics (e.g. energy, latency and throughput) into a global search space?
Topics of interest include, but are not limited to:
- Rapid simulation techniques especially those targeted at new architectures: Multi-cores, 3D-architectures, FPGA based heterogeneous Multi-cores/MPSoC, ...
- Variability and power/energy consumption in performance estimation and simulation techniques.
- High-level abstraction modeling, e.g., Transactional Level Modeling (TLM), Analytical Modeling, Trace-Driven Simulation ?
- Rapid design space exploration (DSE) for heterogeneous and embedded systems.
- Dynamic binary translation for fast simulation and DSE
- Experience reports using existing simulators
- Benchmarking and simulator validation
Important dates:
Submission deadline: Oct 28, 2013
Notification to authors: Nov 20, 2013
Final version of accepted papers: Dec 2, 2013
Paper submission :
Electronic paper submission requires a full paper, up to 8 double-column ACM format pages, including figures and references. Please use the following template when preparing your manuscript: http://www.acm.org/sigs/
The paper submission will be conducted using the EasyChair conference manager. Papers should be submitted in PDF format.
You will find the submission site at: https://www.easychair.org/
Accepted papers will be published in the ACM digital library.
Organizers:
Daniel Gracia P?rez, Thales Research and Technology France, France
Morteza Biglari-Abhari, University of Auckland, New Zealand
Gianluca Palermo, Politecnico di Milano, Italy
Daniel Chillet, Universit? de Rennes 1, France
6th Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools
(http://www.hipeac.net/rapido)
in Vienna, Austria, January, 2014
Held in conjunction with the 9th International Conference on High Performance Embedded Architectures and Compilers (HiPEAC) (http://www.hipeac.net/
==============================
Goal of the Workshop :
The focus of the RAPIDO?14 workshop is on methods and tools for rapid simulation and performance evaluation in embedded and high performance system design. Given continuous advances in chip technology, it is to be expected that future-generation processors will integrate numerous units on a single die, including multiple processor cores, multiple levels of (shared/private) caches or memories, and multiple dedicated accelerators, which will be glued together through a network on-chip (NoC).
The design space is huge though:
- How many cores do we need?
- Should we have a homogeneous or a heterogeneous design?
- When dynamic reconfiguration must be performed?
- How many caches/memories do we need?
- How to choose the instruction set(s) for these cores?
- What are the best code optimizations for a given application?
- How to combine the different metrics (e.g. energy, latency and throughput) into a global search space?
Topics of interest include, but are not limited to:
- Rapid simulation techniques especially those targeted at new architectures: Multi-cores, 3D-architectures, FPGA based heterogeneous Multi-cores/MPSoC, ...
- Variability and power/energy consumption in performance estimation and simulation techniques.
- High-level abstraction modeling, e.g., Transactional Level Modeling (TLM), Analytical Modeling, Trace-Driven Simulation ?
- Rapid design space exploration (DSE) for heterogeneous and embedded systems.
- Dynamic binary translation for fast simulation and DSE
- Experience reports using existing simulators
- Benchmarking and simulator validation
Important dates:
Submission deadline: Oct 28, 2013
Notification to authors: Nov 20, 2013
Final version of accepted papers: Dec 2, 2013
Paper submission :
Electronic paper submission requires a full paper, up to 8 double-column ACM format pages, including figures and references. Please use the following template when preparing your manuscript: http://www.acm.org/sigs/
The paper submission will be conducted using the EasyChair conference manager. Papers should be submitted in PDF format.
You will find the submission site at: https://www.easychair.org/
Accepted papers will be published in the ACM digital library.
Organizers:
Daniel Gracia P?rez, Thales Research and Technology France, France
Morteza Biglari-Abhari, University of Auckland, New Zealand
Gianluca Palermo, Politecnico di Milano, Italy
Daniel Chillet, Universit? de Rennes 1, France
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