A Workshop in conjunction with ISCA 2014
Saturday June 14th 2014, Minneapolis, MN
Call for Papers:
We invite short 4-page papers along the lines of IEEE Computer
Architecture Letters. Papers should focus on the key new ideas and
preliminary evaluations are fine. Accepted papers will be posted on
the workshop webpage and should not preclude later publication at
other conferences and journals.
Important Dates:
Paper submissions due: Friday April 11th, 2014
Notification: Friday April 25th, 2014
Final Paper Due: Monday June 9th, 2014
Workshop Scope:
In recent years, the memory bottleneck has grown and new memory
technologies are emerging to challenge the traditional dominance
of DRAM. DRAM itself has also been evolving, through the development
of 3DS, HBM, HMC, and Wide IO. All of these factors demand novel
memory architectures and organizations, methods of scheduling and
managing memory, and algorithms for maintaining reliable data
storage with unreliable bits. The Memory Forum will bring together
researchers from both academia and industry to discuss advances in
memory architecture, organization, and management. The workshop will
include a few invited talks to educate the audience about upcoming
technologies. The rest of the program will include short
presentations based on submitted papers -- the goal is to provide
feedback to authors on early-stage and exciting ideas. Approaches
to memory management that rely on programming language techniques
may be better suited to the SIGPLAN-sponsored MSPC workshop that is
co-located with PLDI.
Organizers:
Rajeev Balasubramonian, University of Utah
Michael Healy, IBM TJ Watson Research Center
Onur Mutlu, Carnegie Mellon University
Program Committee:
Jung Ho Ahn, Seoul National University
Rajeev Balasubramonian, University of Utah
Ricardo Bianchini, Rutgers University
John Carter, IBM
Mattan Erez, UT Austin
Babak Falsafi, EPFL
Michael Healy, IBM TJ Watson Research Center
Engin Ipek, University of Rochester
Hyesoon Kim, Georgia Tech
Benjamin Lee, Duke University
Gabriel Loh, AMD
Krishna Teja Malladi, Samsung
Jose Martinez, Cornell University
Naveen Muralimanohar, HP Labs
Onur Mutlu, Carnegie Mellon University
Mike O'Connor, NVIDIA, UT Austin
Jong Hoon Oh, SK Hynix
Churoo Park, Samsung
Yanos Sazeides, University of Cyprus
Andre Seznec, IRISA/INRIA
Jeff Stuecheli, IBM
Aniruddha N. Udipi, ARM
Chris Wilkerson, Intel
Jun Yang, University of Pittsburgh
Lixin Zhang, ICT, CAS
Saturday June 14th 2014, Minneapolis, MN
Call for Papers:
We invite short 4-page papers along the lines of IEEE Computer
Architecture Letters. Papers should focus on the key new ideas and
preliminary evaluations are fine. Accepted papers will be posted on
the workshop webpage and should not preclude later publication at
other conferences and journals.
Important Dates:
Paper submissions due: Friday April 11th, 2014
Notification: Friday April 25th, 2014
Final Paper Due: Monday June 9th, 2014
Workshop Scope:
In recent years, the memory bottleneck has grown and new memory
technologies are emerging to challenge the traditional dominance
of DRAM. DRAM itself has also been evolving, through the development
of 3DS, HBM, HMC, and Wide IO. All of these factors demand novel
memory architectures and organizations, methods of scheduling and
managing memory, and algorithms for maintaining reliable data
storage with unreliable bits. The Memory Forum will bring together
researchers from both academia and industry to discuss advances in
memory architecture, organization, and management. The workshop will
include a few invited talks to educate the audience about upcoming
technologies. The rest of the program will include short
presentations based on submitted papers -- the goal is to provide
feedback to authors on early-stage and exciting ideas. Approaches
to memory management that rely on programming language techniques
may be better suited to the SIGPLAN-sponsored MSPC workshop that is
co-located with PLDI.
Organizers:
Rajeev Balasubramonian, University of Utah
Michael Healy, IBM TJ Watson Research Center
Onur Mutlu, Carnegie Mellon University
Program Committee:
Jung Ho Ahn, Seoul National University
Rajeev Balasubramonian, University of Utah
Ricardo Bianchini, Rutgers University
John Carter, IBM
Mattan Erez, UT Austin
Babak Falsafi, EPFL
Michael Healy, IBM TJ Watson Research Center
Engin Ipek, University of Rochester
Hyesoon Kim, Georgia Tech
Benjamin Lee, Duke University
Gabriel Loh, AMD
Krishna Teja Malladi, Samsung
Jose Martinez, Cornell University
Naveen Muralimanohar, HP Labs
Onur Mutlu, Carnegie Mellon University
Mike O'Connor, NVIDIA, UT Austin
Jong Hoon Oh, SK Hynix
Churoo Park, Samsung
Yanos Sazeides, University of Cyprus
Andre Seznec, IRISA/INRIA
Jeff Stuecheli, IBM
Aniruddha N. Udipi, ARM
Chris Wilkerson, Intel
Jun Yang, University of Pittsburgh
Lixin Zhang, ICT, CAS
No comments:
Post a Comment