OCPNBS 6th Special Session on On-Chip Parallel and Network-Based Systems

6^th Special Session on On-Chip Parallel and Network-Based Systems (OCPNBS)

in conjunction with 23rd Euromicro PDP 2015,

http://www.pdp2015.org/specialsessions/ocpnbs/ocpnbs.html

Selected high-quality papers from the session will be considered to appear in 

Elsevier Journal of Computers & Electrical Engineering

General Scope

On-chip parallel and network-based system design to achieve functionality with low energy-speed product requires larger device count SoC design, multi block function design methodology, architectures and energy evaluation schemes. Such systems, which are emerging as the architecture of choice for future high performance processors, require high performance interconnects which are necessary to satisfy the data supply needs of all cores. This session is dedicated to research on on-chip communication technology, architecture, design methods and applications, bringing together scientists and engineers working on on-chip innovations from related research communities, including parallel computer architecture, networking, and embedded systems. Original papers describing new and previously unpublished results are solicited on all aspects of on-chip parallel and networked system technology. Topics of interest include, but are not limited to:

·         On-chip network architecture (topology, routing, arbitration, ...)

·         Network design for 3D stacked logic and memory

·         Processor allocation and scheduling in CMPs   

·         Mapping of applications onto NoCs

·         NoC reliability issues

·         OS and compiler support for NoCs

·         Performance and power issues in NoCs

·         Metrics, benchmarks, and trace analysis for NoCs

·         Multi/many-core workload characterization and evaluation

·         Modeling and simulation of on-chip parallel and networked systems

·         Synthesis, verification, debug and test of SoCs

·         NoC support for memory and cache access

·         SoC and NoC design methodologies and tools

·         Network support for SoC quality of service

·         On-chip systems for FPGAs and structured ASICs

·         NoC support for CMP/MPSoCs

·         Floorplan-aware NoC architecture optimization

·         Application-specific NoC design

·         Networked SoC case studies

·         On-chip parallel programming models and tools

·         Reconfigurable SoCs and NoCs

·         Memory system design and optimizations for SoCs

·         Early reports on system prototypes details

·         SIMD parallel VLSI computing

·         I/O interconnects and support for SoCs

Proceeding and Special Issue

Proceedings will be published by IEEE Computer Society in the same volume of the main track. Authors of accepted papers are expected to register and present their papers at the Conference. Conference proceedings will be indexed, among others, by IEEE explore, DBLP, Scopus ScienceDirect, and ISI Web of Knowledge.

Selected high-quality papers from the session will be considered to appear in Elsevier Journal of Computers & Electrical Engineering

Paper Submissions

Prospective authors should submit a full paper not exceeding 8 pages in the IEEE Conference proceedings format (IEEEtran, double-column, 10pt). Double-bind review: the first page of the paper should contain only the title and abstract; in the reference list, references to the authors’ own work should appear as "omitted for blind review" entries. Manuscript submission

Important Dates

Paper submission: 25th August 2014
Acceptance notification: 25th Oct 2014
Camera ready due: 10th Nov 2014
Conference: 4th - 6th Mar 2015

Organizers

Hamid Sarbazi-Azad (Sharif University of Technology, Iran)

Nader Bagherzadeh (UC-Irvine, USA)

Masoud Daneshtalab (University of Turku, Finland)

Masoumeh Ebrahimi (KTH Royal Institute of Technology, Sweden)