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HiPINEB 2016
The 2nd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era
Barcelona, Spain, March 2016
To be held in conjunction with the HPCA Conference 2016
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*** 4-page short papers are welcome
*** IEEE CPS will edit the workshop proceedings to be submitted to IEEE Xplore and CSDL
*** Workshop's keynote to be given by the Professor Jose Duato, from the Technical University of Valencia, Spain
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ABSTRACT
By the year 2023, High-Performance Computing (HPC) Systems are expected to break the performance barrier of the Exaflop (10^18 FLOPS) while their power consumption is kept at current levels (or increases marginally), what is known as the Exascale challenge. In addition, more storage capacity and data-access speed is demanded to HPC clusters and datacenters to manage and store huge amounts of data produced by software applications, what is known as the Big-Data challenge. Indeed, both the Exascale and Big-Data challenges are driving the technological revolution of this decade, motivating big research and development efforts from industry and academia. In this context, the interconnection network plays an essential role in the architecture of HPC systems and datacenters, as the number of processing or storage nodes to be interconnected in these systems is very likely to grow significantly to meet the higher computing and storage demands. Besides, the capacity of the network links is expected to grow, as the roadmaps of several interconnect standards forecast. Therefore, the interconnection network should provide a high communication bandwidth and low latency, otherwise the network becoming the bottleneck of the entire system. In that regard, many design aspects are considered when it comes to improving the interconnection network performance, such as topology, routing algorithm, power consumption, reliability and fault tolerance, congestion control, programming models, control software, etc.
The main goal of the second HiPINEB workshop is to gather and discuss in a full-day event the latest and most prominent efforts and advances, both from industry and academia, in the design and development of scalable high-performance interconnection networks, especially those oriented to meet the Exascale challenge and Big-data demands.
All researchers and professionals, both from industry and academia, working in the area of interconnection networks for scalable HPC systems and Datacenters are encouraged to submit an original paper to the workshop and to attend this event.
TOPICS OF INTEREST
The list of topics covered by this workshop includes, but is not limited to, the following:
* Interconnect architectures and network technologies for high-speed, low-latency interconnects.
* Scalable network topologies, suitable for interconnecting a huge number of nodes.
* Power saving policies in the interconnect devices and network infrastructure, both at software and hardware level.
* Emerging ideas, work-in-progress and early, high-impact achievements.
* Good practices in the configuration of the network control software.
* Network communication protocols: MPI, RDMA, Hadoop, etc.
* APIs and support for programming models.
* Routing algorithms.
* Quality of Service (QoS).
* Reliability and Fault tolerance.
* Load balancing and traffic scheduling.
* Network Virtualization.
* Congestion Management.
* Applications and Traffic characterization.
* Modeling and simulation tools.
* Performance Evaluation.
Furthermore, short papers in the above topics will be also taken into consideration, as long as they are based on emerging ideas, work-in-progress and early, high-impact achievements.
Note, however, that papers focused on topics that are too far from the design, development and configuration of high-performance interconnects for HPC systems and Datacenters (e.g., mobile networks, intrusion detection, peer-to-peer networks or grid/cloud computing) will be automatically considered as out of scope and rejected without review.
PAPER SUBMISSIONS
Regular and short papers must be in PDF format and should include title, authors and affiliations as well as the e-mail address of the contact author. Submitted regular manuscripts may not exceed 8 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages, including figures, tables, and references. Short papers may not exceed 4 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages. At least one author of the paper must be registered for the conference workshop. The conference style is based on IEEE (available at: http://www.ieee.org/
Authors can buy additional pages in the proceedings. Two extra pages at 100$ each will be allowed for regular papers, and one extra page at 100$ will be allowed for short papers.
HiPINEB manuscript submissions are managed by easyChair. To submit a paper, go to https://easychair.org/
REVIEW PROCESS
Authors are entitled to submit original papers of high technical quality, according to the list of topics described above. Papers will be reviewed based on originality, novelty, technical strength, presentation quality, correctness and relevance to the conference scope. Papers will be published in the HiPINEB proceedings, edited by the IEEE CPS which will be submitted for indexing and inclusion in Xplore and CSDL.
SPECIAL ISSUE
Best papers among those selected for HiPINEB 2016 will be published in a journal Special Issue. Further information will be provided soon.
IMPORTANT DATES
Submission Opens: 15 October 2015
Paper submission due: 18 December 2015
Notification of acceptance: 25 January 2016
Early Registration due: 1 February 2016
Camera-ready papers due: 1 February 2016
Workshop date: 12 March 2016
All deadlines are set at 11:59 p.m. anywhere on Earth
PROGRAM HIGHLIGHTS
* Keynote: Given by the professor Jose Duato (Technical University of Valencia, Spain)
* Technical sessions: Presentation of regular and short papers
* Panel: Panelists to be announced
WORKSHOP ORGANIZATION
Organizers:
* Pedro Javier Garcia, University of Castilla-La Mancha, Spain
* Jesus Escudero-Sahuquillo, Technical University of Valencia, Spain
Program Committee:
* Francisco J. Alfaro, University of Castilla-La Mancha, Spain
* Jose Cano-Reyes, University of Edinburgh, United Kingdom
* Lizhong Chen, Oregon State University, USA
* Reetuparna Das, University of Michigan, USA
* Bruno Farcy, Atos, France
* Holger Fröning, University of Heidelberg, Germany
* Maria Engracia Gomez, Technical University of Valencia, Spain
* Ernst Gunnar Gran, Simula Research Laboratory, Norway
* Ryan E. Grant, Sandia National Laboratories, USA
* John Kim, KAIST, South Korea
* Michihiro Koibuchi, National Institute of Informatics, Japan
* Pedro Lopez, Technical University of Valencia, Spain
* Elad Mentovich, Mellanox Technologies, Israel
* Gaspar Mora, Intel Corporation, USA
* Julio Ortega, University of Granada, Spain
* Dhabaleswar K. Panda, The Ohio State University, USA
* Fabrizio Petrini, IBM Corporation, USA
* Samuel Rodrigo, Oracle Corporation, Norway
* Jose Luis Sanchez, University of Castilla-La Mancha, Spain
* Alex Shpiner, Mellanox Technologies, Israel
* Tor Skeie, University of Oslo, Norway
* Enrique Vallejo, University of Cantabria, Spain
Steering Committee:
* Jose Duato, Technical University of Valencia, Spain
* Francisco Jose Quiles, University of Castilla-La Mancha, Spain
* Torsten Hoefler, ETH Zurich, Switzerland
* Timothy M. Pinkston, University of Southern California, USA
* Eitan Zahavi, Mellanox, Israel
ADDITIONAL INFORMATION
For more information on HiPINEB 2016, or if you have any question, please contact the workshop organizers at jescudero@gap.upv.es or pedrojavier.garcia@uclm.es
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