MULTIPROG-2016 is now accepting short position and regular research papers
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CALL FOR PAPERS
Ninth International Workshop on
Programmability and Architectures for Heterogeneous Multicores
(MULTIPROG-2016)
Held in conjunction with the 11th International Conference on High-Performance
and Embedded Architectures and Compilers (HiPEAC)
Prague, Czech Republic, January 18, 2016
Workshop website: http://research.ac.upc.edu/
Goal of the Workshop
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Computer manufacturers have embarked on the many-core roadmap, promising to add
more and more cores/hardware threads on their chips. The ever-increasing number
of cores and heterogeneity in architectures has placed new burdens on the
programming community. Software needs to be parallelized and optimized for
accelerators such as GPUs in order to take advantage of the new breed of
multi-/many-core computers. As a result, progress in how to easily harness the
computing power of multi-core architectures is in great demand.
The ninth edition of the MULTIPROG workshop aims to bring together researchers
interested in programming models, runtimes, and computer architecture. The
workshop's emphasis is on heterogeneous architectures and covers issues such as:
* How can future parallel programming models improve software productivity?
* How should compilers, runtimes and architectures support programming
models and emerging applications?
* How to design efficient data structures and innovative algorithms?
MULTIPROG is intended for quick publication of early results, work-in-progress,
etc., and is not intended to prevent later publication of extended papers.
Informal proceedings with accepted papers will be made available at the workshop
and online at the workshop’s web page http://research.ac.upc.edu/
Topics of interest
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Papers are sought on topics including, but not limited to:
* Multi-core architectures
o Architectural support for compilers/programming models
o Processor (core) architecture and accelerators, in particular GPUs
o Memory system architecture
o Performance, power, temperature, and reliability issues
* Heterogeneous computing
o Algorithms and data structures for heterogeneous systems
o Applications for heterogeneous computing and real-time graphics
* Programming models for multi-core architectures
o Language extensions
o Run-time systems
o Compiler optimizations and techniques
* Benchmarking of multi-/many-core architectures
o Tools for discovering and understanding parallelism
o Tools for understanding performance and debugging
o Case studies and performance evaluation
Important dates
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Paper submission: November 22, 2015 (AOE)
Author notification: December 11, 2015
Paper submission
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MULTIPROG is now accepting contributions of regular research papers and short position
papers describing early research on emerging topics. When preparing your submission please
adhere to the following format specification:
* Regular research papers: Regular research papers should preferably use LNCS format (up
to 12 pages, not including references). Single column (up to 12 pages) or double column
(up to 6 pages) formats are also accepted.
* Short position papers: Short position papers should preferably use LNCS format (4-6
pages, not including references). Single column (4-6 pages) or double column (2-3 pages)
formats are also accepted. Papers in this category should explicitly indicate "Position
Paper" as part of the title of their manuscript.
The authors of the accepted papers will be requested to provide the final version of their
paper in LNCS format.
Please use one of the templates below:
* Latex template: ftp://ftp.springer.de/pub/tex/
* Word template: ftp://ftp.springer.de/pub/tex/
Organizers
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Miquel Pericàs Chalmers University of Technology Sweden miquelp[at]chalmers.se
Vassilis Papaefstathiou Chalmers University of Technology Sweden vaspap[at]chalmers.se
Oscar Palomar Barcelona Supercomputing Center Spain oscar.palomar[at]bsc.es
Ferad Zyulkyarov Barcelona Supercomputing Center Spain ferad.zyulkyarov[at]bsc.es
Steering committee
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Eduard Ayguade UPC/Barcelona Supercomputing Center Spain eduard[at]ac.upc.edu
Benedict R. Gaster Qualcomm USA bgaster[at]qti.qualcomm.com
Lee Howes Qualcomm USA lhowes[at]qti.qualcomm.com
Per Stenstrom Chalmers University of Technology Sweden pers[at]chalmers.se
Osman Unsal Barcelona Supercomputing Center Spain osman.unsal[at]bsc.es
Program committee
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Abdelhalim Amer Argonne National Lab USA
Ali Jannesari TU Darmstadt Germany
Avi Mendelson Technion Israel
Christos Kotselidis University of Manchester UK
Daniel Goodman Oracle UK
Dong Ping Zhang AMD USA
Håkan Grahn Blekinge TH Sweden
Hans Vandierendonck Queen’s University Belfast UK
Kenjiro Taura University of Tokyo Japan
Luigi Nardi Imperial College London UK
Naoya Maruyama RIKEN AICS Japan
Oscar Plata University of Malaga Spain
Pedro Trancoso University of Cyprus Cyprus
Polyvios Pratikakis FORTH-ICS Greece
Roberto Gioiosa PNNL USA
Ruben Titos BSC Spain
Sasa Tomic IBM Research Switzerland
Simon McIntosh-Smith University of Bristol UK
Timothy G. Mattson Intel USA
Trevor E. Carlson Uppsala University Sweden
Workshop site
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