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==
Call For Papers
International Workshop on Architecture-Aware Simulation and Computing
(AASC 2016)
http://hpcs2016.cisedu.info/2-
sc
WHEN: July 18-22, 2016,
WHERE: The University of Innsbruck, Innsbruck, Austria
DEADLINE: April 21, 2016 (anywhere on earth)
Will take place during The International Conference on High Performance
Computing & Simulation (HPCS 2016) (http://hpcs2016.cisedu.info/)
==============================
==
BACKGROUND AND OBJECTIVES
-------------------------
To keep pace with the performance increase predicted by Moore's Law and to
cope
with energy efficiency requirements, homogeneous/heterogeneous processor
aggregates have been extensively adopted both at the High Performance
Computing
(HPC) and at the embedded system domains.
Realizing the full potential of such systems has become increasingly
challenging
due to: limited parallelization opportunities; reduced memory throughput
and
complex cache hierarchies; limited communication bandwidth; and thermal,
power
and energy constraints. At the same time, because the prevailing HPC and
embedded computing architectures, integrate different types of
co-processors and
accelerator components (e.g., Intel Xeon Phi, GPUs, FPGAs, reconfigurable
SoCs,
etc.), has made the task of developing efficient HPC applications
challenging.
It is widely recognized that next generation HPC and embedded systems can
only
benefit from the hardware's full potential if both processor and
architecture
features are taken into account at all development stages - from the early
algorithmic design to the final implementation stage.
The AASC workshop strives to address all aspects related to these issues,
including, but not limited to:
- Hardware-aware compute/memory-intensive simulations of real-world
problems
in computational science and engineering domains (e.g., applications in
electrical, mechanical, physics, geological, biological, or medical
engineering).
- Architecture-aware approaches for large-scale parallel computing,
including
scheduling, load-balancing and scalability studies.
- Architecture-aware parallelization on HPC platforms, including multi- and
many-core architectures comprising co-processor/accelerator components
(e.g.,
Intel Xeon Phi, GPUs, FPGAs, etc.).
- Architecture-aware approaches for energy-efficient implementations of
HPC or
embedded applications (e.g., ARM, mobile GPUs, reconfigurable SoCs,
etc.).
- Programming models and tool support for parallel heterogeneous platforms
(e.g., CUDA, OpenCL, OpenACC, etc.).
- Software engineering, code optimization, and code generation strategies
for
parallel systems with multi-/many-core processors.
- Performance and memory optimization tools and techniques (including cache
optimization, data reuse, data streaming, etc.) for parallel systems with
multi-core processors.
IMPORTANT DATES
---------------
Paper Submissions: ------------------------------
2016
Acceptance Notification: ------------------------------
2016
Camera Ready Papers and Registration Due by: ----------------- May 15, 2016
Conference Dates: ------------------------------
2016
INSTRUCTIONS FOR PAPER SUBMISSIONS
------------------------------
You are invited to submit original and unpublished research works on the
above
and other topics related to Architecture-Aware Simulation and Computing.
Submitted papers must not have been published or simultaneously submitted
elsewhere.
Two types of papers are allowed. Full papers, whose length must not exceed
8
pages, and short papers, whose length must not exceed 4 pages. Additional
pages
will be charged additional fee.
The papers must be formatted using IEEE's manuscript templates for
conference
proceedings and US Letter size pages and must include up to 6 keywords.
Additional information and style files can be found at:
http://www.ieee.org/
l
Submit the PDF file of your paper to the Workshop paper submission site at:
https://easychair.org/
Each paper will receive a minimum of three reviews. Papers will be selected
based on their originality, relevance, significance, technical clarity and
presentation, and references. At least one of the authors of each accepted
paper
will have to register and attend the HPCS 2016 conference to present the
paper
at the Workshop.
PROCEEDINGS
-----------
Accepted papers will be published in the conference proceedings which will
be
made available at the time of the meeting. Instructions for final
manuscript
format and requirements will be posted on the HPCS 2016 Conference web
site. It
is our intent to have the proceedings formally published in hard and soft
copies
and be available at the time of the conference. The proceedings is
projected to
be included in the IEEE Digital Library and indexed in major indexing
services
accordingly.
If you have any questions about paper submission or the workshop, please
contact
the workshop organizers.
WORKSHOP ORGANIZERS
-------------------
David Parello
Universite de Perpignan, Perpignan, France
David.Parello@univ-perp.fr
George Karypis
University of Minnesota - Twin Cities, Minnesota, USA
karypis@cs.umn.edu
******************************
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If you do not remember your password (which is needed to change these options), you can reset it using the "Unsubscribe or Edit Options" button at the bottom of the page.
()
******************************
sent to . If you'd like to opt out of these
announcements, information on how to unsubscribe is available at the
bottom of this email.]
[Please accept our apologies if you receive multiple copies of this Call
for
Papers (CFP)]
==============================
==
Call For Papers
International Workshop on Architecture-Aware Simulation and Computing
(AASC 2016)
http://hpcs2016.cisedu.info/2-
sc
WHEN: July 18-22, 2016,
WHERE: The University of Innsbruck, Innsbruck, Austria
DEADLINE: April 21, 2016 (anywhere on earth)
Will take place during The International Conference on High Performance
Computing & Simulation (HPCS 2016) (http://hpcs2016.cisedu.info/)
==============================
==
BACKGROUND AND OBJECTIVES
-------------------------
To keep pace with the performance increase predicted by Moore's Law and to
cope
with energy efficiency requirements, homogeneous/heterogeneous processor
aggregates have been extensively adopted both at the High Performance
Computing
(HPC) and at the embedded system domains.
Realizing the full potential of such systems has become increasingly
challenging
due to: limited parallelization opportunities; reduced memory throughput
and
complex cache hierarchies; limited communication bandwidth; and thermal,
power
and energy constraints. At the same time, because the prevailing HPC and
embedded computing architectures, integrate different types of
co-processors and
accelerator components (e.g., Intel Xeon Phi, GPUs, FPGAs, reconfigurable
SoCs,
etc.), has made the task of developing efficient HPC applications
challenging.
It is widely recognized that next generation HPC and embedded systems can
only
benefit from the hardware's full potential if both processor and
architecture
features are taken into account at all development stages - from the early
algorithmic design to the final implementation stage.
The AASC workshop strives to address all aspects related to these issues,
including, but not limited to:
- Hardware-aware compute/memory-intensive simulations of real-world
problems
in computational science and engineering domains (e.g., applications in
electrical, mechanical, physics, geological, biological, or medical
engineering).
- Architecture-aware approaches for large-scale parallel computing,
including
scheduling, load-balancing and scalability studies.
- Architecture-aware parallelization on HPC platforms, including multi- and
many-core architectures comprising co-processor/accelerator components
(e.g.,
Intel Xeon Phi, GPUs, FPGAs, etc.).
- Architecture-aware approaches for energy-efficient implementations of
HPC or
embedded applications (e.g., ARM, mobile GPUs, reconfigurable SoCs,
etc.).
- Programming models and tool support for parallel heterogeneous platforms
(e.g., CUDA, OpenCL, OpenACC, etc.).
- Software engineering, code optimization, and code generation strategies
for
parallel systems with multi-/many-core processors.
- Performance and memory optimization tools and techniques (including cache
optimization, data reuse, data streaming, etc.) for parallel systems with
multi-core processors.
IMPORTANT DATES
---------------
Paper Submissions: ------------------------------
2016
Acceptance Notification: ------------------------------
2016
Camera Ready Papers and Registration Due by: ----------------- May 15, 2016
Conference Dates: ------------------------------
2016
INSTRUCTIONS FOR PAPER SUBMISSIONS
------------------------------
You are invited to submit original and unpublished research works on the
above
and other topics related to Architecture-Aware Simulation and Computing.
Submitted papers must not have been published or simultaneously submitted
elsewhere.
Two types of papers are allowed. Full papers, whose length must not exceed
8
pages, and short papers, whose length must not exceed 4 pages. Additional
pages
will be charged additional fee.
The papers must be formatted using IEEE's manuscript templates for
conference
proceedings and US Letter size pages and must include up to 6 keywords.
Additional information and style files can be found at:
http://www.ieee.org/
l
Submit the PDF file of your paper to the Workshop paper submission site at:
https://easychair.org/
Each paper will receive a minimum of three reviews. Papers will be selected
based on their originality, relevance, significance, technical clarity and
presentation, and references. At least one of the authors of each accepted
paper
will have to register and attend the HPCS 2016 conference to present the
paper
at the Workshop.
PROCEEDINGS
-----------
Accepted papers will be published in the conference proceedings which will
be
made available at the time of the meeting. Instructions for final
manuscript
format and requirements will be posted on the HPCS 2016 Conference web
site. It
is our intent to have the proceedings formally published in hard and soft
copies
and be available at the time of the conference. The proceedings is
projected to
be included in the IEEE Digital Library and indexed in major indexing
services
accordingly.
If you have any questions about paper submission or the workshop, please
contact
the workshop organizers.
WORKSHOP ORGANIZERS
-------------------
David Parello
Universite de Perpignan, Perpignan, France
David.Parello@univ-perp.fr
George Karypis
University of Minnesota - Twin Cities, Minnesota, USA
karypis@cs.umn.edu
******************************
(
If you do not remember your password (which is needed to change these options), you can reset it using the "Unsubscribe or Edit Options" button at the bottom of the page.
()
******************************
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