[Apologies if you got multiple copies of this email. This message is
sent to . If you'd like to opt out of these
announcements, information on how to unsubscribe is available at the
bottom of this email.]
****************************** ****************************** ********************
(https://lists.mcs.anl.gov/ mailman/listinfo/hpc-announce
If you do not remember your password (which is needed to change these options), you can reset it using the "Unsubscribe or Edit Options" button at the bottom of the page.
(https://lists.mcs.anl.gov/ mailman/listinfo/hpc-announce)
.
****************************** ****************************** ********************
sent to . If you'd like to opt out of these
announcements, information on how to unsubscribe is available at the
bottom of this email.]
IEEE Micro - Special Issue Call for Papers
Architectures for the Post-Moore Era
Submission deadline: 6 January 2017
Publication: July/August 2017
Propelling computer performance beyond the scaling limits of Moore’s
Law will likely require a comprehensive rethinking of
technologies—from materials to devices, circuits, and
architectures. How will advances in quantum, neuromorphic,
approximate, probabilistic, and stochastic computing affect
performance? This special issue of IEEE Micro will examine
architectures and processor designs for a post-Moore era.
Papers should address questions such as:
• What technologies might prevail in the post-Moore era?
• What architectural abstractions should represent traditional
concepts like hierarchical parallelism and multi-tier data
locality?
• What architectural abstractions should represent new concepts like
variable precision, approximate solutions, and resource
tradeoff directives?
• Can microarchitectural changes hide these technologies, or are novel
ISAs required?
Topics of interest include:
• technology trends and predictions.
• microarchitectures employing 2.5D and 3D stacking and monolithic 3D
integration.
• alternative memory systems and memory-centric architectures.
• quantum, neuromorphic, reconfigurable, and superconducting
microarchitectures.
• new electronics based on carbon-nanotubes, memristors, graphene, and
so on.
• silicon photonics and optical networks for computer architectures.
• performance studies, modeling, simulation, and emulation of
post-Moore processors.
Submission Procedure
Log in to ScholarOne Manuscripts and submit your
manuscript. Acceptable file formats are Microsoft Word document and
PDF. Please direct ScholarOne questions to the IEEE Micro magazine
assistant (micro-ma@computer.org). Manuscripts should not exceed 5,000
words, including a maximum of 12 references, with each average¬ sized
figure counting as 250 words. Please include all figures and tables,
as well as a cover page with author contact information (name, postal
address, phone, fax, and email address) and a 200¬-word
abstract. Accepted articles will be edited for structure, style,
clarity, and readability. For more information, please visit the IEEE
Micro author guidelines. Submitted manuscripts must not have been
previously published or submitted for publication elsewhere, and all
manuscripts must be cleared for publication. All conference papers
must have at least 30 percent new content compared to the original.
Guest Editors
• Jeffrey S. Vetter, Oak Ridge National Laboratory
• Erik P. DeBenedictis, Sandia National Laboratories
• Thomas M. Conte, Georgia Institute of Technology
Important Dates (all in 2017)
• 6 Jan: Submissions due
• 26 Feb: Decision made
• 22 Mar: Revised papers due
• 22 Apr: Final versions due
Questions?
Contact the guest editors at mi4-2017@computer.org, or the EiC at
# # #
******************************
(https://lists.mcs.anl.gov/
If you do not remember your password (which is needed to change these options), you can reset it using the "Unsubscribe or Edit Options" button at the bottom of the page.
(https://lists.mcs.anl.gov/
******************************
No comments:
Post a Comment