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For the workshop, we will prepare hand-outs with the accepted papers. The revised versions will be published after the conference in the workshop proceedings of Euro-Par 2017, part of the LNCS series of Springer.
Further Information
-------------------
See the ROME'17 website at http://www.rome.eonerc.
Important Dates
---------------
* May 5, 2017: Submission deadline
* June 16, 2017: Notification of acceptance
* July 21, 2017: Workshop paper (for informal workshop proceedings)
* October 3, 2017: Workshop camera-ready papers due
Workshop Organizers
-------------------
* Stefan Lankes, Institute for Automation of Complex Power Systems,
E.ON Energy Research Center, RWTH Aachen University, Germany
* Carsten Clauss, ParTec Cluster Competence Center GmbH, Germany
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==============================
The 5th Workshop on
Runtime and Operating Systems for the Many-core Era
(
August 28/29, 2017, Santiago de Compostela, Spain
held in conjunction with
Euro-Par 2017, August 28 - September 1, 2017
Santiago de Compostela, Spain
http://www.rome.eonerc.rwth-
==============================
Background
----------
Since the beginning of the multicore era, parallel processing has become prevalent across the board. However, in order to continue a performance increase according to Moore's Law, a next step needs to be taken: away from common multicores towards innovative many-core architectures. Such systems, equipped with a significant higher amount of cores per chip than multicores, pose challenges in both hardware and software design. On the hardware side, complex on-chip networks, scratchpads, hybrid memory cubes, non-volatile memory and stacked memory, as well as deep cache-hierarchies and novel cache-coherence strategies will enrich the current research areas in the future.
However, the ROME workshop focuses on the software side because without complying system software, runtime and operating system support, all these new hardware facilities cannot be exploited. Hence, the new challenges in hardware/software co-design are to step beyond traditional approaches and to wage new programming models and operating system designs in order to exploit the theoretically available performance of future hardware as effectively and power-aware as possible.
Topics
------
This year, too, authors from all related disciplines are invited to submit unpublished papers regarding software for novel many-core hardware architectures. The call for papers especially emphasizes on the challenges and research questions arising from the upcoming generation of heterogeneous and/or massive parallel systems stepping towards a many-core dominated exascale era. The topics of interest include, but are not limited to:
* New approaches for operating systems on novel many-core architectures
* Operating system extensions for addressing many-core related issues
* Many-core aware runtime support for large-scale applications
* Bare-metal programming and system software for many-cores
* Dealing with legacy software on novel many-core architectures
* Virtualization to deal with hardware limitations on many-cores
* Support for interactivity with and between many-core applications
* Message-passing interfaces and middleware for many-core systems
* Heterogeneity- and/or hierarchy-aware many-core middleware
* Concepts and methods for exploiting deep memory hierarchies
* Operating system extensions for non-volatile memory support
* Software stacks for new concepts of compute acceleration on many-cores
* Interfaces for performance and power analysis on many-core systems
* Runtime support for power-aware many-core computing
Paper Submission
The 5th Workshop on
Runtime and Operating Systems for the Many-core Era
(
August 28/29, 2017, Santiago de Compostela, Spain
held in conjunction with
Euro-Par 2017, August 28 - September 1, 2017
Santiago de Compostela, Spain
http://www.rome.eonerc.rwth-
==============================
Background
----------
Since the beginning of the multicore era, parallel processing has become prevalent across the board. However, in order to continue a performance increase according to Moore's Law, a next step needs to be taken: away from common multicores towards innovative many-core architectures. Such systems, equipped with a significant higher amount of cores per chip than multicores, pose challenges in both hardware and software design. On the hardware side, complex on-chip networks, scratchpads, hybrid memory cubes, non-volatile memory and stacked memory, as well as deep cache-hierarchies and novel cache-coherence strategies will enrich the current research areas in the future.
However, the ROME workshop focuses on the software side because without complying system software, runtime and operating system support, all these new hardware facilities cannot be exploited. Hence, the new challenges in hardware/software co-design are to step beyond traditional approaches and to wage new programming models and operating system designs in order to exploit the theoretically available performance of future hardware as effectively and power-aware as possible.
Topics
------
This year, too, authors from all related disciplines are invited to submit unpublished papers regarding software for novel many-core hardware architectures. The call for papers especially emphasizes on the challenges and research questions arising from the upcoming generation of heterogeneous and/or massive parallel systems stepping towards a many-core dominated exascale era. The topics of interest include, but are not limited to:
* New approaches for operating systems on novel many-core architectures
* Operating system extensions for addressing many-core related issues
* Many-core aware runtime support for large-scale applications
* Bare-metal programming and system software for many-cores
* Dealing with legacy software on novel many-core architectures
* Virtualization to deal with hardware limitations on many-cores
* Support for interactivity with and between many-core applications
* Message-passing interfaces and middleware for many-core systems
* Heterogeneity- and/or hierarchy-aware many-core middleware
* Concepts and methods for exploiting deep memory hierarchies
* Operating system extensions for non-volatile memory support
* Software stacks for new concepts of compute acceleration on many-cores
* Interfaces for performance and power analysis on many-core systems
* Runtime support for power-aware many-core computing
Paper Submission
----------------
Submissions in PDF format should be between 10–12 pages in the Springer LNCS style, which can be downloaded from the Springer Web site ftp://ftp.springer.de/
Upload your submission to our submission server (https://www.easychair.
Submissions in PDF format should be between 10–12 pages in the Springer LNCS style, which can be downloaded from the Springer Web site ftp://ftp.springer.de/
Upload your submission to our submission server (https://www.easychair.
For the workshop, we will prepare hand-outs with the accepted papers. The revised versions will be published after the conference in the workshop proceedings of Euro-Par 2017, part of the LNCS series of Springer.
Further Information
-------------------
See the ROME'17 website at http://www.rome.eonerc.
Important Dates
---------------
* May 5, 2017: Submission deadline
* June 16, 2017: Notification of acceptance
* July 21, 2017: Workshop paper (for informal workshop proceedings)
* October 3, 2017: Workshop camera-ready papers due
Workshop Organizers
-------------------
* Stefan Lankes, Institute for Automation of Complex Power Systems,
E.ON Energy Research Center, RWTH Aachen University, Germany
* Carsten Clauss, ParTec Cluster Competence Center GmbH, Germany
--
Dr. rer. nat. Stefan Lankes
Institute for Automation of Complex Power Systems
E.ON Energy Research Center, RWTH Aachen University
Mathieustraße 10
52074 Aachen, Germany
Phone: +49-241-80-49740
E-Mail: slankes@eonerc.rwth-aachen.de
Dr. rer. nat. Stefan Lankes
Institute for Automation of Complex Power Systems
E.ON Energy Research Center, RWTH Aachen University
Mathieustraße 10
52074 Aachen, Germany
Phone: +49-241-80-49740
E-Mail: slankes@eonerc.rwth-aachen.de
******************************
(https://lists.mcs.anl.gov/
If you do not remember your password (which is needed to change these options), you can reset it using the "Unsubscribe or Edit Options" button at the bottom of the page.
(https://lists.mcs.anl.gov/
******************************
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