http://www.islped.org
The International Symposium on Low Power Electronics and Design (ISLPED)
(http://www.islped.org) is the premier forum for presentation of recent
advances in all aspects of low power design and technologies, ranging
from process and circuit technologies, simulation and synthesis tools,
to system level design and optimization. Specific topics include, but
are not limited to, the following two main areas, each with three sub-areas:
1.1.Technologies and Digital Circuits
Emerging logic/memory technologies and applications; Low power device
and interconnect design; Low power low leakage circuits; Memory
circuits; 3-D technologies; Cooling technologies; Battery technologies;
Variation-tolerant design; Temperature-aware and reliable design.
1.2. Logic and Microarchitecture Design
Processor core design; Cache and register file design; Memory
Architectures; Logic and RTL design; Arithmetic and signal processing
circuits; Encryption technologies; Asynchronous design.
1.3. Analog, MEMS, Mixed Signal and Imaging Electronics
RF circuits; Wireless; MEMS circuits; AD/DA Converters; I/O
circuits; Mixed signal circuits; Imaging circuits; Circuits to support
emerging technologies and platforms; DC-DC converters.
2.1. CAD & Design Tools
Energy estimation and optimization tools that operate at the
physical, circuit/gate level, RT level, behavioral level, and
algorithmic levels; Links to other metrics: variability, reliability,
temperature.
2.2. System Design and Methodologies
Microprocessor, DSP and embedded systems design; FPGA and ASIC designs;
System-level power- and thermal-aware design; System-level reliability-
and variability-aware design; Systems for Emerging applications
2.3. Software Design and Optimization
Power- and thermal-aware software design, scheduling, and management;
Application-level optimizations; Wireless and sensor networks; Software
for emerging applications.
*TECHNICAL PAPER SUBMISSIONS DEADLINE: Abstract registration: March 8,
2013; Full paper: March 15, 2013.*
Submissions should be full-length papers of up to 6 pages
(double-column, IEEE Transactions/Conference format, available at
template download
<http://www.ieee.org/
including all illustrations, tables, references and an abstract of no
more than 100 words. Papers exceeding the six-page limit will not be
reviewed. *Submission must be anonymous*: papers identifying the authors
and/or with explicit references to their prior work will be
automatically rejected. Electronic submission in *pdf format* only via
the web is required.
Submitted papers must describe original work that will not be announced
or published prior to the Symposium and that is not being considered or
under review by another conference at the same time. Accepted papers
will be presented in one of two parallel tracks: one focusing on
architectures, circuits and technologies, the other on design tools and
systems and software design for low power. Notification of paper
acceptance will be mailed by *May 20, 2013* and the camera-ready version
of the paper will be due by *June 20, 2013*. Accepted papers will be
published in the Symposium Proceedings and included in the ACM Digital
Library. Authors of a few selected papers from the Symposium will also
be given an opportunity to submit enhanced versions of their papers for
publication in a special issue of a reputed journal. ISLPED???13 will
present two Best Paper Awards based on the ratings of reviewers and an
invited panel of judges.
*INVITED TALK, PANEL, AND TUTORIAL PROPOSALS DEADLINE: Received by March
16, 2013.*
There will be several invited talks by industry and academic thought
leaders on key issues in low power electronics and design. All invited
talks will be in plenary sessions. The Symposium may also include
embedded tutorials to provide attendees with the necessary background to
follow recent research results, as well as panel discussions on future
directions and design/technology alternatives in low power electronics
and design.
Technical Program Chairs:
Yuan Xie, Penn State / AMD Research yuanxie@cse.psu.edu
Tanay Karnik, Intel Labs tanay.karnik@gmail.com
The International Symposium on Low Power Electronics and Design (ISLPED)
(http://www.islped.org) is the premier forum for presentation of recent
advances in all aspects of low power design and technologies, ranging
from process and circuit technologies, simulation and synthesis tools,
to system level design and optimization. Specific topics include, but
are not limited to, the following two main areas, each with three sub-areas:
1.1.Technologies and Digital Circuits
Emerging logic/memory technologies and applications; Low power device
and interconnect design; Low power low leakage circuits; Memory
circuits; 3-D technologies; Cooling technologies; Battery technologies;
Variation-tolerant design; Temperature-aware and reliable design.
1.2. Logic and Microarchitecture Design
Processor core design; Cache and register file design; Memory
Architectures; Logic and RTL design; Arithmetic and signal processing
circuits; Encryption technologies; Asynchronous design.
1.3. Analog, MEMS, Mixed Signal and Imaging Electronics
RF circuits; Wireless; MEMS circuits; AD/DA Converters; I/O
circuits; Mixed signal circuits; Imaging circuits; Circuits to support
emerging technologies and platforms; DC-DC converters.
2.1. CAD & Design Tools
Energy estimation and optimization tools that operate at the
physical, circuit/gate level, RT level, behavioral level, and
algorithmic levels; Links to other metrics: variability, reliability,
temperature.
2.2. System Design and Methodologies
Microprocessor, DSP and embedded systems design; FPGA and ASIC designs;
System-level power- and thermal-aware design; System-level reliability-
and variability-aware design; Systems for Emerging applications
2.3. Software Design and Optimization
Power- and thermal-aware software design, scheduling, and management;
Application-level optimizations; Wireless and sensor networks; Software
for emerging applications.
*TECHNICAL PAPER SUBMISSIONS DEADLINE: Abstract registration: March 8,
2013; Full paper: March 15, 2013.*
Submissions should be full-length papers of up to 6 pages
(double-column, IEEE Transactions/Conference format, available at
template download
<http://www.ieee.org/
including all illustrations, tables, references and an abstract of no
more than 100 words. Papers exceeding the six-page limit will not be
reviewed. *Submission must be anonymous*: papers identifying the authors
and/or with explicit references to their prior work will be
automatically rejected. Electronic submission in *pdf format* only via
the web is required.
Submitted papers must describe original work that will not be announced
or published prior to the Symposium and that is not being considered or
under review by another conference at the same time. Accepted papers
will be presented in one of two parallel tracks: one focusing on
architectures, circuits and technologies, the other on design tools and
systems and software design for low power. Notification of paper
acceptance will be mailed by *May 20, 2013* and the camera-ready version
of the paper will be due by *June 20, 2013*. Accepted papers will be
published in the Symposium Proceedings and included in the ACM Digital
Library. Authors of a few selected papers from the Symposium will also
be given an opportunity to submit enhanced versions of their papers for
publication in a special issue of a reputed journal. ISLPED???13 will
present two Best Paper Awards based on the ratings of reviewers and an
invited panel of judges.
*INVITED TALK, PANEL, AND TUTORIAL PROPOSALS DEADLINE: Received by March
16, 2013.*
There will be several invited talks by industry and academic thought
leaders on key issues in low power electronics and design. All invited
talks will be in plenary sessions. The Symposium may also include
embedded tutorials to provide attendees with the necessary background to
follow recent research results, as well as panel discussions on future
directions and design/technology alternatives in low power electronics
and design.
Technical Program Chairs:
Yuan Xie, Penn State / AMD Research yuanxie@cse.psu.edu
Tanay Karnik, Intel Labs tanay.karnik@gmail.com
No comments:
Post a Comment