The 20th IEEE International Symposium on High-Performance Computer Architecture (HPCA'14)

The 20th IEEE International Symposium on High-Performance Computer
Architecture (HPCA'14)
February 2014 - Orlando, FL, (collocated with CGO-2014 and PPoPP-2014)
http://hpca20.ece.ufl.edu/

The International Symposium on High-Performance Computer Architecture
provides a high-quality forum for scientists and engineers to present
their latest research findings in this rapidly-changing field. Authors
are invited to submit papers on all aspects of high-performance
computer architecture.

Topics of interest include, but are not limited to:
- Processor, cache, and memory architectures
- Parallel computer architectures
- Multi-core architectures
- Impact of technology on architecture
- Power-efficient architectures and techniques
- Dependable/secure architectures
- High-performance I/O systems
- Embedded and re-configurable architectures
- Interconnect and network interface architectures
- Architectures for cloud-based HPC and data centers
- Innovative hardware/software trade-offs
- Impact of compilers and system software on architecture
- Performance modeling and evaluation
- Architectures for emerging technology and applications

Authors should submit an abstract by Tuesday, September 3, 2013, 11:59
PM EDT. They should submit the full version of the paper by Friday,
September 6, 2013, 11:59 PM EDT. No extensions will be granted. Papers
should be submitted for double-blind review. We anticipate making a
Best Paper award; all papers will be evaluated based on their novelty,
fundamental insights, and potential for long-term impact. New-idea
papers are encouraged. Submission issues should be directed to the
program chair at <enright@eecg.toronto.edu>. Workshop and tutorial
submissions should be directed to the workshop and tutorial co-chairs
(nsatish@umich.edu, jmwu@ustc.edu.cn). HPCA-20 will host an Industrial
Paper Session presenting novel insights from industry.

Important Dates
* Abstract deadline: September 3, 2013, 11:59 PM EDT
* Paper deadline: September 6, 2013, 11:59 PM EDT
* Workshop and tutorial proposals due: September 7, 2013
* Notification of paper outcome: November 13, 2013


General Chair: Tao Li, University of Florida

Program Chair: Natalie Enright Jerger, University of Toronto

Program Committee:
Murali Annavaram, University of Southern California
Todd Austin, University of Michigan
Rajeev Balasubramonian, University of Utah
Trey Cain, Qualcomm Research-Raleigh
Ramon Canal, UPC
Tom Conte, Georgia Tech
Chita Das, Penn State
Joe Devietti, University of Pennsylvania
Lieven Eeckhout, Ghent University
Babak Falsafi, EPFL
Antonio Gonzalez, Intel/UPC
James Hoe, Carnegie Mellon University
Lisa Hsu, Qualcomm Research-Raleigh
Hillery Hunter, IBM Research
Ravi Iyer, Intel
Vijay Janapa Reddi, University of Texas
Russ Joseph, Northwestern University
Ulya Karpuzcu, University of Minnesota
John Kim, KAIST
Nam Sung Kim, University of Wisconsin
Ruby Lee, Princeton University
Gabriel Loh, AMD Research
Ahmed Louri, Arizona
Jos? Mart?nez, Cornell University
Ravi Rajwar, Intel
Partha Ranganathan, HP
Steve Reinhardt, AMD Research
Karu Sankaralingam, University of Wisconsin
Josh Simons, VMware
Daniel Sorin, Duke University
Viji Srinivasan, IBM Research
Per Stenstrom, Chalmers
Lingjia Tang, UCSD
Michael Taylor, UCSD
Thomas Wenisch, University of Michigan
David Wentzlaff, Princeton University
Carole-Jean Wu, Arizona State
Yuan Xie, AMD Research China/Penn State
Sudhakar Yalamachili, Georgia Tech
Jun Yang, University of Pittsburgh

Steering Committee:
Lixin Zhang, ICT/Chinese Academy of Sciences
Dean Tullsen, University of California, San Diego
David Christie, AMD
David Koppelman, Louisiana State University
David Brooks, Harvard University
Laxmi Bhuyan, University of California, Riverside
David Kaeli, Northeastern University
Yale Patt, University of Texas at Austin
Josep Torrellas, University of Illinois, Urbana-Champaign