IA^3 Workshop on Irregular Applications: Architectures & Algorithms
------------------------------
http://cass-mt.pnnl.gov/
Sunday, November 17, 2013
Colorado Convention Center
Denver, Colorado USA
To be held in conjunction with:
SC13 - The International Conference for High Performance Computing, Networking, Storage and Analysis
http://sc13.supercomputing.org
In collaboration with SIGHPC http://www.sighpc.org<https://
---------
Theme
---------
Many data intensive scientific applications are by nature irregular. They may present irregular data structures, irregular control flow or irregular communication. Current supercomputing systems are organized around components optimized for data locality and regular computation. Developing irregular applications on them demands a substantial effort, and often leads to poor performance. However, executing irregular applications efficiently will be a key requirement for future systems.
The solutions needed to address irregular applications challenges can only come by considering the problem from all perspectives: from micro- to system-architectures, from compilers to languages, from libraries to runtimes, from algorithm design to data characteristics. Only collaborative efforts among researchers with different expertise, including end users, domain experts, and computer scientists, could lead to significant breakthroughs. This workshop aims at bringing together scientists with all these different backgrounds to discuss, define and design methods and technologies for efficiently supporting irregular applications on current and future systems.
------------------
Call for Papers
------------------
A broad class of applications is irregular. Irregular applications present unpredictable memory access patterns, control structures, and/or network transfers. They typically use pointer or linked lists-based data structures such as graphs and trees, often present fine-grained synchronization and communication, and generally operate on very large data sets. They have a significant degree of latent parallelism, which is however difficult to fully exploit because of their complex behavior. Beside performance, another significant concern for emerging irregular applications is the size of the datasets. In fact, modern applications operate on massive amount of data, often unstructured, which are very difficult to partition and easily generate load unbalance.
Current high performance architectures rely on data locality, regular computations, structured data and easily partitionable datasets. They do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, because of their limits with fine-grained communication and synchronization. Irregular applications pertain both to well established and emerging fields, such as Computer Aided Design (CAD), bioinformatics, semantic graph databases, social network analysis, and computer security. Addressing the issues of these applications on current and future architectures will become critical to solve the scientific challenges of the next few years.
This workshop seeks to explore solutions for supporting efficient design, development and execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to:
* Micro- and System-architectures
* Network and memory architectures
* Manycore, heterogeneous and custom architectures (Tilera, GPUs, FPGAs)
* Modeling and evaluation of architectures
* Innovative algorithmic techniques
* Parallelization techniques and data structures
* Languages and programming models
* Library and runtime support
* Compiler and analysis techniques
* Case studies of irregular applications (e.g. Semantic Graph Databases, Data Mining, Security, Bioinformatics)
Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers.
--------------------
Important Dates
--------------------
* Abstract Submission: 2 September 2013 (23:59 PST)
* Paper Submission: 9 September 2013 (23:59 PST)
* Notification of Acceptance: 9 October 2013
* Workshop: 17 November 2013
------------------------------
Paper Submission Guidelines
------------------------------
Submission site: http://www.easychair.org/
All submissions should be in double-column, single-spaced letter format, using 10-point size fonts, with at least one inch margins on each side. Submitted manuscripts may not exceed eight pages in length for regular papers and four pages for position papers including figures, tables and references. For any question, please contact the organizers.
----------------
Organization
----------------
Workshop Chairs:
Antonino Tumeo, PNNL (antonino.tumeo@pnnl.gov<
Oreste Villa, NVIDIA (oreste.villa@nvidia.com<
John Feo, PNNL (john.feo@pnnl.gov<mailto:john
Simone Secchi, Universit? di Cagliari (simone.secchi@diee.unica.it<
Publicity Chair: Alessandro Morari, Universitat Polit?cnica de Catalunya and PNNL
Submission Chair: Silvia Lovergine, Politecnico di Milano and PNNL
Publication Chair: Vito Giovanni Castellana, Politecnico di Milano and PNNL
Program Committee:
Keren Bergman, Columbia University, USA
David Brooks, Harvard University, USA
Bryan Catanzaro, NVIDIA, USA
Selim Ciraci, Pacific Northwest National Laboratory, USA
Georgi Gaydadjiev, Chalmers University, Sweden
Mahantesh Halappanavar, Pacific Northwest National Laboratory, USA
John Leidel, Cray, USA
Kamesh Madduri, The Pennsylvania State University, USA
Joseph Manzano, Pacific Northwest National Laboratory, USA
Matteo Monchiero, Intel, USA
Walid Najjar, University of California, Riverside, USA
Gianluca Palermo, Politecnico di Milano, Italy
Fabrizio Petrini, IBM TJ Watson, USA
Keshav Pingali, University of Texas, Austin, USA
John Shalf, Lawrence Berkeley National Laboratory, USA
Pedro Trancoso, University of Cyprus, Cyprus
Mateo Valero, Barcelona Supercomputing Center, Spain
------------------------------
--
Alessandro Morari
Post Master Research Associate
Pacific Northwest National Laboratory
MSIN: J4-30
Battelle Boulevard 902
Richland, WA 99352
+1 509-372-5944
------------------------------
http://cass-mt.pnnl.gov/
Sunday, November 17, 2013
Colorado Convention Center
Denver, Colorado USA
To be held in conjunction with:
SC13 - The International Conference for High Performance Computing, Networking, Storage and Analysis
http://sc13.supercomputing.org
In collaboration with SIGHPC http://www.sighpc.org<https://
---------
Theme
---------
Many data intensive scientific applications are by nature irregular. They may present irregular data structures, irregular control flow or irregular communication. Current supercomputing systems are organized around components optimized for data locality and regular computation. Developing irregular applications on them demands a substantial effort, and often leads to poor performance. However, executing irregular applications efficiently will be a key requirement for future systems.
The solutions needed to address irregular applications challenges can only come by considering the problem from all perspectives: from micro- to system-architectures, from compilers to languages, from libraries to runtimes, from algorithm design to data characteristics. Only collaborative efforts among researchers with different expertise, including end users, domain experts, and computer scientists, could lead to significant breakthroughs. This workshop aims at bringing together scientists with all these different backgrounds to discuss, define and design methods and technologies for efficiently supporting irregular applications on current and future systems.
------------------
Call for Papers
------------------
A broad class of applications is irregular. Irregular applications present unpredictable memory access patterns, control structures, and/or network transfers. They typically use pointer or linked lists-based data structures such as graphs and trees, often present fine-grained synchronization and communication, and generally operate on very large data sets. They have a significant degree of latent parallelism, which is however difficult to fully exploit because of their complex behavior. Beside performance, another significant concern for emerging irregular applications is the size of the datasets. In fact, modern applications operate on massive amount of data, often unstructured, which are very difficult to partition and easily generate load unbalance.
Current high performance architectures rely on data locality, regular computations, structured data and easily partitionable datasets. They do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, because of their limits with fine-grained communication and synchronization. Irregular applications pertain both to well established and emerging fields, such as Computer Aided Design (CAD), bioinformatics, semantic graph databases, social network analysis, and computer security. Addressing the issues of these applications on current and future architectures will become critical to solve the scientific challenges of the next few years.
This workshop seeks to explore solutions for supporting efficient design, development and execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to:
* Micro- and System-architectures
* Network and memory architectures
* Manycore, heterogeneous and custom architectures (Tilera, GPUs, FPGAs)
* Modeling and evaluation of architectures
* Innovative algorithmic techniques
* Parallelization techniques and data structures
* Languages and programming models
* Library and runtime support
* Compiler and analysis techniques
* Case studies of irregular applications (e.g. Semantic Graph Databases, Data Mining, Security, Bioinformatics)
Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers.
--------------------
Important Dates
--------------------
* Abstract Submission: 2 September 2013 (23:59 PST)
* Paper Submission: 9 September 2013 (23:59 PST)
* Notification of Acceptance: 9 October 2013
* Workshop: 17 November 2013
------------------------------
Paper Submission Guidelines
------------------------------
Submission site: http://www.easychair.org/
All submissions should be in double-column, single-spaced letter format, using 10-point size fonts, with at least one inch margins on each side. Submitted manuscripts may not exceed eight pages in length for regular papers and four pages for position papers including figures, tables and references. For any question, please contact the organizers.
----------------
Organization
----------------
Workshop Chairs:
Antonino Tumeo, PNNL (antonino.tumeo@pnnl.gov<
Oreste Villa, NVIDIA (oreste.villa@nvidia.com<
John Feo, PNNL (john.feo@pnnl.gov<mailto:john
Simone Secchi, Universit? di Cagliari (simone.secchi@diee.unica.it<
Publicity Chair: Alessandro Morari, Universitat Polit?cnica de Catalunya and PNNL
Submission Chair: Silvia Lovergine, Politecnico di Milano and PNNL
Publication Chair: Vito Giovanni Castellana, Politecnico di Milano and PNNL
Program Committee:
Keren Bergman, Columbia University, USA
David Brooks, Harvard University, USA
Bryan Catanzaro, NVIDIA, USA
Selim Ciraci, Pacific Northwest National Laboratory, USA
Georgi Gaydadjiev, Chalmers University, Sweden
Mahantesh Halappanavar, Pacific Northwest National Laboratory, USA
John Leidel, Cray, USA
Kamesh Madduri, The Pennsylvania State University, USA
Joseph Manzano, Pacific Northwest National Laboratory, USA
Matteo Monchiero, Intel, USA
Walid Najjar, University of California, Riverside, USA
Gianluca Palermo, Politecnico di Milano, Italy
Fabrizio Petrini, IBM TJ Watson, USA
Keshav Pingali, University of Texas, Austin, USA
John Shalf, Lawrence Berkeley National Laboratory, USA
Pedro Trancoso, University of Cyprus, Cyprus
Mateo Valero, Barcelona Supercomputing Center, Spain
------------------------------
--
Alessandro Morari
Post Master Research Associate
Pacific Northwest National Laboratory
MSIN: J4-30
Battelle Boulevard 902
Richland, WA 99352
+1 509-372-5944
No comments:
Post a Comment