Call for Paper
5th On-Chip Parallel and Network-Based Systems (OCPNBS)
in conjunction with 22nd Euromicro PDP 2014, Turin, Italy, 12-14 Feb. 2014
http://www.pdp2014.org/
with a special issue in
Elsevier's Integration, the VLSI Journal<http://www.journals.
Deadline extension: August 25th
General Scope
In order to achieve functionality with low energy speed product, on-chip parallel and network-based system design requires larger device, multi block functions, and energy evaluation schemes. Such systems, which are emerging as the architecture of choice for future high performance processors, require efficient interconnect which are necessary to satisfy the data supply needs of all cores.
This session is dedicated to research on on-chip communication technology, architecture, design methods and applications, bringing together scientists and engineers working on on-chip innovations from related research communities, including parallel computer architecture, networking, and embedded systems. Original papers describing new and previously unpublished results are solicited on all aspects of on-chip parallel and networked system technology. Topics of interest include, but are not limited to:
* On-chip network architecture (topology, routing, arbitration, ...)
* 3D stacked logic and memory
* Processor allocation and scheduling in many/multi-core processors
* Mapping
* Reliability and Reconfigurability issues
* OS and compiler support
* Performance and power issues
* Metrics, benchmarks, and trace analysis
* Workload characterization & evaluation
* Modeling and simulation
* Synthesis, verification, debug & test
* Design methodologies and tools
* Quality of service
* FPGAs and structured ASICs
* Application-specific design issues
* Parallel programming models and tools
* Memory system design and optimizations
Proceeding and Special Issue
Proceedings will be published by IEEE Computer Society in the same volume of the main track. Authors of accepted papers are expected to register and present their papers at the Conference. Conference proceedings will be indexed, among others, by IEEE explore, DBLP, Scopus ScienceDirect, and ISI Web of Knowledge.
Selected high-quality papers from the session will be considered to appear in Integration, the VLSI Journal<http://www.journals.
Paper Submissions
Prospective authors should submit a full paper not exceeding 8 pages in the IEEE Conference proceedings format (IEEEtran, double-column, 10pt). Double-bind review: the first page of the paper should contain only the title and abstract; in the reference list, references to the authors' own work should appear as "omitted for blind review" entries.
Important Dates
Submission deadline: 31st July 2013 ? 25th August 2013
Notification of acceptance: 7th October 2013
Camera ready: 31st October 2013
Organizers
Hamid Sarbazi-Azad (Sharif University of Technology, Iran)
Nader Bagherzadeh (UC-Irvine, USA)
Masoud Daneshtalab (University of Turku, Finland)
5th On-Chip Parallel and Network-Based Systems (OCPNBS)
in conjunction with 22nd Euromicro PDP 2014, Turin, Italy, 12-14 Feb. 2014
http://www.pdp2014.org/
with a special issue in
Elsevier's Integration, the VLSI Journal<http://www.journals.
Deadline extension: August 25th
General Scope
In order to achieve functionality with low energy speed product, on-chip parallel and network-based system design requires larger device, multi block functions, and energy evaluation schemes. Such systems, which are emerging as the architecture of choice for future high performance processors, require efficient interconnect which are necessary to satisfy the data supply needs of all cores.
This session is dedicated to research on on-chip communication technology, architecture, design methods and applications, bringing together scientists and engineers working on on-chip innovations from related research communities, including parallel computer architecture, networking, and embedded systems. Original papers describing new and previously unpublished results are solicited on all aspects of on-chip parallel and networked system technology. Topics of interest include, but are not limited to:
* On-chip network architecture (topology, routing, arbitration, ...)
* 3D stacked logic and memory
* Processor allocation and scheduling in many/multi-core processors
* Mapping
* Reliability and Reconfigurability issues
* OS and compiler support
* Performance and power issues
* Metrics, benchmarks, and trace analysis
* Workload characterization & evaluation
* Modeling and simulation
* Synthesis, verification, debug & test
* Design methodologies and tools
* Quality of service
* FPGAs and structured ASICs
* Application-specific design issues
* Parallel programming models and tools
* Memory system design and optimizations
Proceeding and Special Issue
Proceedings will be published by IEEE Computer Society in the same volume of the main track. Authors of accepted papers are expected to register and present their papers at the Conference. Conference proceedings will be indexed, among others, by IEEE explore, DBLP, Scopus ScienceDirect, and ISI Web of Knowledge.
Selected high-quality papers from the session will be considered to appear in Integration, the VLSI Journal<http://www.journals.
Paper Submissions
Prospective authors should submit a full paper not exceeding 8 pages in the IEEE Conference proceedings format (IEEEtran, double-column, 10pt). Double-bind review: the first page of the paper should contain only the title and abstract; in the reference list, references to the authors' own work should appear as "omitted for blind review" entries.
Important Dates
Submission deadline: 31st July 2013 ? 25th August 2013
Notification of acceptance: 7th October 2013
Camera ready: 31st October 2013
Organizers
Hamid Sarbazi-Azad (Sharif University of Technology, Iran)
Nader Bagherzadeh (UC-Irvine, USA)
Masoud Daneshtalab (University of Turku, Finland)
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