Elsevier Journal of Computers & Electrical Engineering
Special Issue on Network-on-Chip Architectures
Modern Systems-on-Chip (SoCs) today contains hundreds of cores, including, processors,
co-processors, accelerators, application-specific IPs, peripherals, memories, reconfigurable
logic, and even analog blocks. We are now entered in the so called many-core era. The
International Technology Roadmap for Semiconductors foresees that the number of
Processing Elements (PEs) that will be integrated into a SoC will be in the order of thousand
within the 2020. As the number of communicating elements increases, there is a need for an
efficient, scalable and reliable communication infrastructure. As technology geometries shrink
to the deep submicron regime, however, the communication delay and power consumption of
global interconnections become the major bottleneck. The Network-on-Chip (NoC) design
paradigm, based on a modular packet-switched mechanism, can address many of the on-chip
communication issues such as performance limitations of long interconnects, and integration
of large number of PEs on a chip.
The goal of the special issue is to present innovative ideas and solutions related to design
and implementation of many-core systems-on-chip. This special issue will focus on issues
related to design, analysis and testing of on-chip networks. We also look for new type
of NoC-based computing paradigms inspired by biological systems to solve hard
computational problems such as learning, recognition, and complex decision making.
Topics of interest include, but are not limited to:
* Topologies selection and synthesis for NoCs and MPSoCs
* Routing algorithms and router micro-architectures
* QoS in on-chip communication
* Mapping of cores to NoC slots
* Power and energy issues
* Fault tolerance and reliability issues
* Memory architectures for NoC
* Dynamic on-chip network reconfiguration
* Modeling and evaluation of on-chip networks
* On-chip interconnection network simulators and emulators
* Analytical analysis methods for NoC performance and other properties
* Verification, debug and test of NoC
* 3D NoC architectures
* Emerging technologies and new design paradigms
* Industrial case studies of SoC designs using the NoC paradigm
* Heterogeneity
* NoC-based Brain-like computing device
* NoC-based platform for DNA sequencing
* HPC application and computer servers
Selected papers from NoCArc'2013 workshop will be invited to submit an extension version
of their paper. In addition, any other high quality submission that fits the topics of this
Special Issue is welcome. All invited papers will be subjected to the same rigorous review
process as the regular submissions to this Special Issue. Submitted articles must not have
been previously published or currently submitted for publication elsewhere. For work that
has been published previously in a workshop or conference, it is required that submissions
to the special issue have at least 40% new content. Submissions that do not meet this
requirement will be rejected without review. The papers should be submitted via the
Manuscript Central website and should adhere to standard formatting requirements.
All manuscripts should be submitted via the online submission at
http://ees.elsevier.com/
as "SI: noc". All manuscripts should comply with the journal's Guide for Authors:
http://www.elsevier.com/wps/
Schedule:
Paper submission deadline: February. 15, 2014
Review decisions: May. 15, 2014
Revisions due: June. 15, 2014
Notification of acceptance: August. 15, 2014
Final manuscript due: September. 15, 2014
Publication: January. 15, 2015
Guest Editors (in alphabetical order):
Masoud Daneshtalab, University of Turku, Finland (http://users.utu.fi/masdan/)
Terrence Mak, The Chinese University of Hong Kong, China (http://www.staff.ncl.ac.uk/
Maurizio Palesi, Kore University of Enna, Italy (http://www.unikore.it/
Special Issue on Network-on-Chip Architectures
Modern Systems-on-Chip (SoCs) today contains hundreds of cores, including, processors,
co-processors, accelerators, application-specific IPs, peripherals, memories, reconfigurable
logic, and even analog blocks. We are now entered in the so called many-core era. The
International Technology Roadmap for Semiconductors foresees that the number of
Processing Elements (PEs) that will be integrated into a SoC will be in the order of thousand
within the 2020. As the number of communicating elements increases, there is a need for an
efficient, scalable and reliable communication infrastructure. As technology geometries shrink
to the deep submicron regime, however, the communication delay and power consumption of
global interconnections become the major bottleneck. The Network-on-Chip (NoC) design
paradigm, based on a modular packet-switched mechanism, can address many of the on-chip
communication issues such as performance limitations of long interconnects, and integration
of large number of PEs on a chip.
The goal of the special issue is to present innovative ideas and solutions related to design
and implementation of many-core systems-on-chip. This special issue will focus on issues
related to design, analysis and testing of on-chip networks. We also look for new type
of NoC-based computing paradigms inspired by biological systems to solve hard
computational problems such as learning, recognition, and complex decision making.
Topics of interest include, but are not limited to:
* Topologies selection and synthesis for NoCs and MPSoCs
* Routing algorithms and router micro-architectures
* QoS in on-chip communication
* Mapping of cores to NoC slots
* Power and energy issues
* Fault tolerance and reliability issues
* Memory architectures for NoC
* Dynamic on-chip network reconfiguration
* Modeling and evaluation of on-chip networks
* On-chip interconnection network simulators and emulators
* Analytical analysis methods for NoC performance and other properties
* Verification, debug and test of NoC
* 3D NoC architectures
* Emerging technologies and new design paradigms
* Industrial case studies of SoC designs using the NoC paradigm
* Heterogeneity
* NoC-based Brain-like computing device
* NoC-based platform for DNA sequencing
* HPC application and computer servers
Selected papers from NoCArc'2013 workshop will be invited to submit an extension version
of their paper. In addition, any other high quality submission that fits the topics of this
Special Issue is welcome. All invited papers will be subjected to the same rigorous review
process as the regular submissions to this Special Issue. Submitted articles must not have
been previously published or currently submitted for publication elsewhere. For work that
has been published previously in a workshop or conference, it is required that submissions
to the special issue have at least 40% new content. Submissions that do not meet this
requirement will be rejected without review. The papers should be submitted via the
Manuscript Central website and should adhere to standard formatting requirements.
All manuscripts should be submitted via the online submission at
http://ees.elsevier.com/
as "SI: noc". All manuscripts should comply with the journal's Guide for Authors:
http://www.elsevier.com/wps/
Schedule:
Paper submission deadline: February. 15, 2014
Review decisions: May. 15, 2014
Revisions due: June. 15, 2014
Notification of acceptance: August. 15, 2014
Final manuscript due: September. 15, 2014
Publication: January. 15, 2015
Guest Editors (in alphabetical order):
Masoud Daneshtalab, University of Turku, Finland (http://users.utu.fi/masdan/)
Terrence Mak, The Chinese University of Hong Kong, China (http://www.staff.ncl.ac.uk/
Maurizio Palesi, Kore University of Enna, Italy (http://www.unikore.it/
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