Do you know ACM TACO 2.0?
Over the last two years ACM TACO (ACM Transactions on Architecture and Code Optimization, http://taco.acm.org/) has dramatically optimized its internal processes. Today, the average turnaround time from submission to first response is 43 days which is 1.5 months. Most accepted manuscripts went through two rounds of reviews to reach a final decision only 5 months after submission. Accepted manuscripts are immediately published in the ACM digital library. Hence, excellent manuscripts can make it from submission to the digital library in about 3 months; papers needing a major revision will make it to the digital library in about 6 months. The ACM TACO acceptance rate after two review rounds is 27%. We call this “ACM TACO 2.0”. Attached at the end of this mail are the titles of the papers printed since January 2015 in ACM TACO.
ACM TACO 2.0 has a review cycle and an acceptance rate which is competitive with the best ACM conferences, but without the inconvenient non-negotiable submission deadlines, and with the advantage of being able to revise a paper based on the detailed review reports by carefully selected reviewers, and of being published as soon as it is accepted. On top of that, authors of original work papers get an open invitation to present their paper at the yearly HiPEAC conference, which is the premier European network event on topics central to ACM TACO, attended by more than 631 scientists in 2015. We already have 10 accepted papers for the January 2016 conference in Prague (https://www.hipeac.org/2016/
For the 2014 ACM TACO 2.0 issues, we are calling for high-quality manuscripts on topics included, but not limited to:
· Computer system architectures and processor architectures, including multiprocessors and multithreaded computers
· Interaction of operating systems, compilers, programming languages, and architecture
· Feedback-Directed Software/Hardware Optimization
· Dynamic compilation, adaptive execution, and continuous profiling/optimization.
· Virtual machine, binary translation hardware, and software optimizations
· Compiler optimizations that exploit instruction level parallelism, such as software pipelining, global scheduling, register allocation, and memory disambiguation
· Advanced software and hardware speculation, prediction, and predication techniques.
· High-performance microarchitecture innovation (e.g., VLIW, superscalar, multithreaded, etc.)
· Architectures and compilers for embedded processors, application specific processors and DSPs, including network and router architectures
· Memory system optimization
· Parallel processing
· Architecture or compiler-based power and energy optimization
· Application characterization and architectural implications
· Performance evaluation and measurement of real systems
· Papers of interest to the SIGMICRO, SIGARCH, and SIGPLAN community
There is no deadline but manuscripts are processed on a first-come-first-served basis. Submit your best work viahttp://mc.manuscriptcentral.
Prof. Koen De Bosschere
ACM TACO Editor-in-Chief
Prof. Per Stenström
ACM TACO Senior Associate Editor
Recently published papers
Volume 11 Issue 4, January 2015
by Cedric Nugteren, Henk Corporaal
by Jue Wang, Xiangyu Dong, Yuan Xie
by Rakesh Komuravelli, Sarita V. Adve, Ching-Tsun Chou
by Gabriel Rodríguez, Juan Touriño, Mahmut T. Kandemir
Art 39: Topological Characterization of Hamming and Dragonfly Networks and Its Implications on Routing
by Cristóbal Camarero, Enrique Vallejo, Ramón Beivide
by Hanbin Yoon, Justin Meza, Naveen Muralimanohar, Norman P. Jouppi, Onur Mutlu
by Nathanael Prémillieu, André Seznec
by Zheng Wang, Dominik Grewe, Michael F. P. O’boyle
by Dan He, Fang Wang, Hong Jiang, Dan Feng, Jing Ning Liu, Wei Tong, Zheng Zhang
by Eri Rubin, Ely Levy, Amnon Barak, Tal Ben-Nun
by Alessandro Cilardo, Luca Gallo
by Jan Kasper Martinsen, Håkan Grahn, Anders Isberg
by Quentin Colombet, Florian Brandner, Alain Darte
by Jawad Haj-Yihia, Yosi Ben Asher, Efraim Rotem, Ahmad Yasin, Ran Ginosar
by Hong-Phuc Trinh, Marc Duranton, Michel Paindavoine
by Maximilien B. Breughe, Stijn Eyerman, Lieven Eeckhout
Art 51: Mitigating Prefetcher-Caused Pollution Using Informed Caching Policies for Prefetched Blocks
by Vivek Seshadri, Samihan Yedkar, Hongyi Xin, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry
by George Matheou, Paraskevas Evripidou
Art 53: GP-SIMD Processing-in-Memory
by Amir Morad, Leonid Yavits, Ran Ginosar
by Thomas Schaub, Simon Moll, Ralf Karrenberg, Sebastian Hack
by Zhenman Fang, Sanyam Mehta, Pen-Chung Yew, Antonia Zhai, James Greensky, Gautham Beeraka, Binyu Zang
by Chi Ching Chi, Mauricio Alvarez-Mesa, Ben Juurlink
by Fabio Luporini, Ana Lucia Varbanescu, Florian Rathgeber, Gheorghe-Teodor Bercea, J. Ramanujam, by by David A. Ham, Paul H. J. Kelly
by Xing Zhou, María J. Garzarán, David A. Padua
by Leo Porter, Michael A. Laurenzano, Ananta Tiwari, Adam Jundt, William A. Ward, Jr., Roy Campbell, Laura Carrington
by Xin Tong, Toshihiko Koju, Motohiro Kawahito, Andreas Moshovos
by Martin Kong, Antoniu Pop, Louis-Noël Pouchet, R. Govindarajan, Albert Cohen, P. Sadayappan
by Nicolas Melot, Christoph Kessler, Jörg Keller, Patrick Eitschberger
by Wenjia Ruan, Yujie Liu, Michael Spear
by Zia Ul Huda, Ali Jannesari, Felix Wolf
by Heiner Litz, Ricardo J. Dias, David R. Cheriton
by Helge Bahmann, Nico Reissmann, Magnus Jahre, Jan Christian Meyer
by Venmugil Elango, Naser Sedaghati, Fabrice Rastello, Louis-Noël Pouchet, J. Ramanujam, Radu by by Teodorescu, P. Sadayappan
Volume 12 Issue 1, March 2015 (volume in progress)
by Christopher Zimmer, Frank Mueller
by Beayna Grigorian, Glenn Reinman
Art 3: Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor
by Anup Holey, Vineeth Mekkat, Pen-Chung Yew, Antonia Zhai
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