==============================
AsHES 2016 - CALL FOR PAPERS
==============================
The Sixth International Workshop on Accelerators and Hybrid Exascale Systems (AsHES)
http://www.mcs.anl.gov/events/
May 23rd, 2016
To be held in conjunction with
30th IEEE International Parallel and Distributed Processing Symposium
Chicago Hyatt Regency, Chicago, Illinois, USA
Important Dates (AoE)
==============================
Paper Submission: Jan. 08, 2016
Paper Notification: Feb. 18, 2016
Camera-Ready: Feb. 25, 2016
Workshop Scope and Goals
==============================
Current and emerging systems are deployed with heterogeneous architectures and accelerators
of more than one type (e.g. GPGPU, Intel® Xeon Phi(tm), FPGA) along with hybrid processors of
both lightweight and heavyweight cores (e.g APU, big.LITTLE). Such architectures also comprise
hybrid memory systems equipped with stacked/hierarchical memory and non-volatile memory in
addition to regular DRAM. Programming such a system can be a real challenge along with locality,
scheduling, load balancing, concurrency and so on.
This workshop focuses on understanding the implications of accelerators and heterogeneous
designs on the hardware systems, porting applications, performing compiler optimizations, and
developing programming environments for current and emerging systems. It seeks to ground
accelerator research through studies of application kernels or whole applications on such
systems, as well as tools and libraries that improve the performance and productivity of
applications on these systems.
The goal of this workshop is to bring together researchers and practitioners who are involved in
application studies for accelerators and other heterogeneous systems, to learn the opportunities
and challenges in future design trends for HPC applications and systems.
Topics of interest for workshop submissions include (but are not limited to):
* Strategies for programming heterogeneous systems using high-level models such as
OpenMP, OpenACC, low-level models such as OpenCL, CUDA;
* Methods and tools to tackle challenges in scientific computing at extreme scale;
* Strategies for application behavior characterization and performance optimization for
accelerators;
* Techniques for optimizing kernels for execution on GPGPU, Intel® Xeon Phi™, and future
heterogeneous platforms;
* Models of application performance on heterogeneous and accelerated HPC systems;
* Compiler Optimizations and tuning heterogeneous systems including parallelization, loop
transformation, locality optimizations, Vectorization;
* Implications of workload characterization in heterogeneous and accelerated architecture
design;
* Benchmarking and performance evaluation for accelerators;
* Tools and techniques to address both performance and correctness to assist application
development for accelerators and heterogeneous processors;
* System software techniques to abstract application domain-specific functionalities for
accelerators;
Papers Submission Guidelines
==============================
Papers should present original research and should provide sufficient background material to
make them accessible to the broader community.
Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point
size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references.
See the style templates for latex or word for details.
Submissions will be judged based on relevance, significance, originality, correctness and clarity.
Submission site: https://easychair.org/
Journal Special Issue
==============================
The best papers of AsHES 2016 will be included in a Special Issue on TBD of the
Elsevier International Journal on Parallel Computing (PARCO), edited by Sunita Chandrasekaran
and Antonio J. Peña. This special issue is dedicated for the papers accepted in the AsHES
workshop. The submission to this special issue is by invitation only.
Steering Committee
==============================
Pavan Balaji, Argonne National Laboratory, USA
Yunquan Zhang, Chinese Academy of Sciences, China
Satoshi Matsuoka, Tokyo Institute of Technology, Japan
Jiayuan Meng, Argonne National Laboratory, USA
Xiaosong Ma, Qatar Computing Research Institute, Qatar
Barbara Chapman, University of Houston, USA
Guang R. Gao, University of Delaware, USA
Xinmin Tian, Intel, USA
Michael Wong, IBM, Canada
General Chair
==============================
James Dinan, Intel Corporation
Program Chair and Co-Chairs
==============================
Wenguang Chen, Tsinghua University, China
Sunita Chandrasekaran, University of Delaware, USA
Antonio J. Peña, Barcelona Supercomputing Center, Spain
Program Committee
==============================
Sangmin Seo, Argonne National Laboratory, USA
Piotr Luszczek, University of Tennessee Knoxville, USA
Anthony Danalis, University of Tennessee, USA
Gabriele Jost, Intel Corporation, USA
Jeff Hammond, Intel Labs, USA
Seeyong Lee, Oak Ridge National Laboratories, USA
John Lidel, Texas Tech University, USA
James Beyer, Cray Inc., USA
Kamesh Madduri, The Pennsylvania State University, USA
Mahantesh M Halappanavar, Pacific Northwest National Laboratory, USA
Stephen Olivier, Sandia Nationl Lab, USA
Guido Juckeland, TU Dresden, Germany
Matthias Muller, TU Aachen, Germany
Barry Rountree, Lawrence Livermore National Laboratory, USA
Hennry Jin, NASA, USA
Dong Li, University of Calfornia, Merced, USA
Khaled Hamidouche, The Ohio State University, USA
Huimin Cui, Institute of Computing Technology, CAS
Xipeng Shen, North Carolina State University, USA
Bronis de Supinski, Lawrence Livermore National Laboratory, USA
Hao Wang, Virginia Tech, USA
Naoya Maruyama, RIKEN AICS
Siva Kumar Sastry Hari, NVIDIA Corporation, USA
Guangyu Sun, Peking University, China
Sriram Krishnamoorthy, Pacific Northwest National Laboratory, USA
Nacho Navarro, UPC- Univesity Politecnica de Catalunya, Spain
Kelly Shaw, University of Richmond, USA
Yongpeng Zhang, Stone Ridge Technology, USA
Fangfang Xia, Argonne National Laboratory, USA
Questions?
==============================
Please send any queries about the AsHES workshop to ashes@mcs.anl.gov
WARNING / LEGAL TEXT: This message is intended only for the use of the individual or entity to which it is addressed and may contain information which is privileged, confidential, proprietary, or exempt from disclosure under applicable law. If you are not the intended recipient or the person responsible for delivering the message to the intended recipient, you are strictly prohibited from disclosing, distributing, copying, or in any way using this message. If you have received this communication in error, please notify the sender and destroy and delete any copies you may have received.
http://www.bsc.es/disclaimer
AsHES 2016 - CALL FOR PAPERS
==============================
The Sixth International Workshop on Accelerators and Hybrid Exascale Systems (AsHES)
http://www.mcs.anl.gov/events/
May 23rd, 2016
To be held in conjunction with
30th IEEE International Parallel and Distributed Processing Symposium
Chicago Hyatt Regency, Chicago, Illinois, USA
Important Dates (AoE)
==============================
Paper Submission: Jan. 08, 2016
Paper Notification: Feb. 18, 2016
Camera-Ready: Feb. 25, 2016
Workshop Scope and Goals
==============================
Current and emerging systems are deployed with heterogeneous architectures and accelerators
of more than one type (e.g. GPGPU, Intel® Xeon Phi(tm), FPGA) along with hybrid processors of
both lightweight and heavyweight cores (e.g APU, big.LITTLE). Such architectures also comprise
hybrid memory systems equipped with stacked/hierarchical memory and non-volatile memory in
addition to regular DRAM. Programming such a system can be a real challenge along with locality,
scheduling, load balancing, concurrency and so on.
This workshop focuses on understanding the implications of accelerators and heterogeneous
designs on the hardware systems, porting applications, performing compiler optimizations, and
developing programming environments for current and emerging systems. It seeks to ground
accelerator research through studies of application kernels or whole applications on such
systems, as well as tools and libraries that improve the performance and productivity of
applications on these systems.
The goal of this workshop is to bring together researchers and practitioners who are involved in
application studies for accelerators and other heterogeneous systems, to learn the opportunities
and challenges in future design trends for HPC applications and systems.
Topics of interest for workshop submissions include (but are not limited to):
* Strategies for programming heterogeneous systems using high-level models such as
OpenMP, OpenACC, low-level models such as OpenCL, CUDA;
* Methods and tools to tackle challenges in scientific computing at extreme scale;
* Strategies for application behavior characterization and performance optimization for
accelerators;
* Techniques for optimizing kernels for execution on GPGPU, Intel® Xeon Phi™, and future
heterogeneous platforms;
* Models of application performance on heterogeneous and accelerated HPC systems;
* Compiler Optimizations and tuning heterogeneous systems including parallelization, loop
transformation, locality optimizations, Vectorization;
* Implications of workload characterization in heterogeneous and accelerated architecture
design;
* Benchmarking and performance evaluation for accelerators;
* Tools and techniques to address both performance and correctness to assist application
development for accelerators and heterogeneous processors;
* System software techniques to abstract application domain-specific functionalities for
accelerators;
Papers Submission Guidelines
==============================
Papers should present original research and should provide sufficient background material to
make them accessible to the broader community.
Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point
size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references.
See the style templates for latex or word for details.
Submissions will be judged based on relevance, significance, originality, correctness and clarity.
Submission site: https://easychair.org/
Journal Special Issue
==============================
The best papers of AsHES 2016 will be included in a Special Issue on TBD of the
Elsevier International Journal on Parallel Computing (PARCO), edited by Sunita Chandrasekaran
and Antonio J. Peña. This special issue is dedicated for the papers accepted in the AsHES
workshop. The submission to this special issue is by invitation only.
Steering Committee
==============================
Pavan Balaji, Argonne National Laboratory, USA
Yunquan Zhang, Chinese Academy of Sciences, China
Satoshi Matsuoka, Tokyo Institute of Technology, Japan
Jiayuan Meng, Argonne National Laboratory, USA
Xiaosong Ma, Qatar Computing Research Institute, Qatar
Barbara Chapman, University of Houston, USA
Guang R. Gao, University of Delaware, USA
Xinmin Tian, Intel, USA
Michael Wong, IBM, Canada
General Chair
==============================
James Dinan, Intel Corporation
Program Chair and Co-Chairs
==============================
Wenguang Chen, Tsinghua University, China
Sunita Chandrasekaran, University of Delaware, USA
Antonio J. Peña, Barcelona Supercomputing Center, Spain
Program Committee
==============================
Sangmin Seo, Argonne National Laboratory, USA
Piotr Luszczek, University of Tennessee Knoxville, USA
Anthony Danalis, University of Tennessee, USA
Gabriele Jost, Intel Corporation, USA
Jeff Hammond, Intel Labs, USA
Seeyong Lee, Oak Ridge National Laboratories, USA
John Lidel, Texas Tech University, USA
James Beyer, Cray Inc., USA
Kamesh Madduri, The Pennsylvania State University, USA
Mahantesh M Halappanavar, Pacific Northwest National Laboratory, USA
Stephen Olivier, Sandia Nationl Lab, USA
Guido Juckeland, TU Dresden, Germany
Matthias Muller, TU Aachen, Germany
Barry Rountree, Lawrence Livermore National Laboratory, USA
Hennry Jin, NASA, USA
Dong Li, University of Calfornia, Merced, USA
Khaled Hamidouche, The Ohio State University, USA
Huimin Cui, Institute of Computing Technology, CAS
Xipeng Shen, North Carolina State University, USA
Bronis de Supinski, Lawrence Livermore National Laboratory, USA
Hao Wang, Virginia Tech, USA
Naoya Maruyama, RIKEN AICS
Siva Kumar Sastry Hari, NVIDIA Corporation, USA
Guangyu Sun, Peking University, China
Sriram Krishnamoorthy, Pacific Northwest National Laboratory, USA
Nacho Navarro, UPC- Univesity Politecnica de Catalunya, Spain
Kelly Shaw, University of Richmond, USA
Yongpeng Zhang, Stone Ridge Technology, USA
Fangfang Xia, Argonne National Laboratory, USA
Questions?
==============================
Please send any queries about the AsHES workshop to ashes@mcs.anl.gov
-- Antonio J. Peña, PhD Senior Researcher Barcelona Supercomputing Center http://www.bsc.es/about-bsc/staff-directory/pena-antonio
WARNING / LEGAL TEXT: This message is intended only for the use of the individual or entity to which it is addressed and may contain information which is privileged, confidential, proprietary, or exempt from disclosure under applicable law. If you are not the intended recipient or the person responsible for delivering the message to the intended recipient, you are strictly prohibited from disclosing, distributing, copying, or in any way using this message. If you have received this communication in error, please notify the sender and destroy and delete any copies you may have received.
http://www.bsc.es/disclaimer
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