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(Please accept our apologies for multiple postings of
this announcement)
Paper submission: 25
September 2016
Acceptance notification: 25 October 2016
Camera ready due: 20 November 2016
Conference: 6-8 March 2017
Special Session on On-Chip Parallel and Network-Based Systems (OCPNBS)
in conjunction with 25th Euromicro PDP 2017,
To be held in St. Petersburg, March 6-8, 2017
General Scope
On-chip parallel and network-based system design
to achieve functionality with low energy-speed product requires larger device
count SoC design, multi block function design methodology, architectures and
energy evaluation schemes. Such systems, which are emerging as the architecture
of choice for future high performance processors, require high performance
interconnects which are necessary to satisfy the data supply needs of all
cores. This session is dedicated to research on on-chip communication
technology, architecture, design methods and applications, bringing together
scientists and engineers working on on-chip innovations from related research
communities, including parallel computer architecture, networking, and embedded
systems. Original papers describing new and previously unpublished results are
solicited on all aspects of on-chip parallel and networked system technology.
Topics of interest include, but are not limited to:
- On-chip network architecture (topology, routing, arbitration, ...)
- Network design for 3D stacked logic and memory
- Processor allocation and scheduling in CMPs
- Mapping of applications onto NoCs
- NoC reliability issues
- OS and compiler support for NoCs
- Performance and power issues in NoCs
- Metrics, benchmarks, and trace analysis for NoCs
- Multi/many-core workload characterization and evaluation
- Modeling and simulation of on-chip parallel and networked systems
- Synthesis, verification, debug and test of SoCs
- NoC support for memory and cache access
- SoC and NoC design methodologies and tools
- Network support for SoC quality of service
- On-chip systems for FPGAs and structured ASICs
- NoC support for CMP/MPSoCs
- Floorplan-aware NoC architecture optimization
- Application-specific NoC design
- Networked SoC case studies
- On-chip parallel programming models and tools
- Reconfigurable SoCs and NoCs
- Memory system design and optimizations for SoCs
- Early reports on system prototypes details
- SIMD parallel VLSI computing
- I/O interconnects and support for SoCs
and other
related topic
Proceeding and Special Issue
The accepted papers will be published in the IEEE Computer Society Press
proceedings together with the proceedings of PDP 2017.
Paper Submissions: Prospective authors
should submit a full paper not exceeding 8 pages (double-column, 10pt) to the
OCPNBS Special Session through the EasyChair
conference submission system.
Acceptance notification: 25 October 2016
Camera ready due: 20 November 2016
Conference: 6-8 March 2017
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