Call for Papers
7th Workshop on Productivity and Performance
held in conjunction with Euro-Par 2014, Porto, Portugal
August 25 or 26, 2014
http://www.vi-hps.org/
Submission Deadline: May 30th 2014
==============================
Driven by current trends in microprocessor design, the number of
processor cores and hardware threads available on modern
supercomputers grows rapidly from generation to generation while the
amount of memory per core will be decreasing. To keep pace,
applications need to harness much higher degrees of parallelism while
ensuring efficient use of the underlying computing resources, which
can be highly concurrent many-core systems or heterogeneous
accelerator architectures (or a combination of both). Additionally,
applications must adhere to additional constraints, in particular with
respect to power consumption (both peak and average power) and
resilience.
Writing codes that run correctly and efficiently on such complex
systems is extraordinarily challenging. At the same time, applications
themselves are becoming more complex as well, which can be seen in
emerging scale- bridging applications, the integration of
fault-tolerance and uncertainty quantification, or advances in
algorithms. Combined, these trends place higher and higher demands on
the application development process and thus require adequate tool
support for debugging and performance analysis. The PROPER workshop
will serve as a forum to present novel work on scalable methods and
tools for high-performance computing. The workshop covers parallel
program development and analysis, debugging, correctness checking, and
performance measurement and evaluation. Further topics include the
integration of tools with compilers and the overall development
environment, as well as success stories reporting application
performance, scalability, reliability, power and energy optimization,
or productivity improvements that have been achieved using tools.
The workshop is supported by the Virtual Institute - High Productivity
Supercomputing (VI-HPS), an initiative to promote the development and
integration of HPC programming tools.
Workshop Topics
- Tools and tool approaches for parallel program development and
analysis
- Infrastructure for building parallel program development
and analysis tools
- Correctness checking and program verification
- Performance and power measurements and evaluation
- Success stories about optimization or parallel scalability
achieved using tools
Important Dates
Note: the deadlines are synchronized across all EuroPar workshops
- May 30th: submission deadline for full papers
- July 4th: notification of acceptance
- July 30th: camera ready papers due
- October 3rd: final paper versions due for Springer proceedings
Program Committee
(tentative list)
- Andreas Kn?pfer, TU Dresden (chair)
- Denis Barthou, INRIA
- David B?hme, German Research School for Simulation Sciences
- Karl F?rlinger, LMU M?nchen
- Michael Gerndt, TU M?nchen
- Kevin Huck, University of Oregon
- Koji Inoue, Kyushu University
- Ignacio Laguna, Lawrence Livermore National Laboratory
- John Mellor-Crummey, Rice University
- Matthias M?ller, RWTH Aachen University
- Shirley Moore, University of Texas at El Paso
- Martin Schulz, Lawrence Livermore National Laboratory
- Nathan Tallent, Pacific Northwest National Laboratory
- Jan Treibig, RRZE, Friedrich-Alexander-Universit?
- Anh Vo, Microsoft
- Felix Wolf, German Research School for Simulation Sciences
- Brian Wylie, J?lich Supercomputing Centre
Contact
Jos? Gracia
High Performance Computing Center Stuttgart (HLRS)
University of Stuttgart
Email gracia@hlrs.de
--
Dr. Jose Gracia email: gracia@hlrs.de
HLRS, Uni Stuttgart http://www.hlrs.de/people/
Nobelstrasse 19 phone: +49 711 685 87208
70569 Stuttgart fax: +49 711 685 65832
Germany pgp key ID: FBDADD6F
7th Workshop on Productivity and Performance
held in conjunction with Euro-Par 2014, Porto, Portugal
August 25 or 26, 2014
http://www.vi-hps.org/
Submission Deadline: May 30th 2014
==============================
Driven by current trends in microprocessor design, the number of
processor cores and hardware threads available on modern
supercomputers grows rapidly from generation to generation while the
amount of memory per core will be decreasing. To keep pace,
applications need to harness much higher degrees of parallelism while
ensuring efficient use of the underlying computing resources, which
can be highly concurrent many-core systems or heterogeneous
accelerator architectures (or a combination of both). Additionally,
applications must adhere to additional constraints, in particular with
respect to power consumption (both peak and average power) and
resilience.
Writing codes that run correctly and efficiently on such complex
systems is extraordinarily challenging. At the same time, applications
themselves are becoming more complex as well, which can be seen in
emerging scale- bridging applications, the integration of
fault-tolerance and uncertainty quantification, or advances in
algorithms. Combined, these trends place higher and higher demands on
the application development process and thus require adequate tool
support for debugging and performance analysis. The PROPER workshop
will serve as a forum to present novel work on scalable methods and
tools for high-performance computing. The workshop covers parallel
program development and analysis, debugging, correctness checking, and
performance measurement and evaluation. Further topics include the
integration of tools with compilers and the overall development
environment, as well as success stories reporting application
performance, scalability, reliability, power and energy optimization,
or productivity improvements that have been achieved using tools.
The workshop is supported by the Virtual Institute - High Productivity
Supercomputing (VI-HPS), an initiative to promote the development and
integration of HPC programming tools.
Workshop Topics
- Tools and tool approaches for parallel program development and
analysis
- Infrastructure for building parallel program development
and analysis tools
- Correctness checking and program verification
- Performance and power measurements and evaluation
- Success stories about optimization or parallel scalability
achieved using tools
Important Dates
Note: the deadlines are synchronized across all EuroPar workshops
- May 30th: submission deadline for full papers
- July 4th: notification of acceptance
- July 30th: camera ready papers due
- October 3rd: final paper versions due for Springer proceedings
Program Committee
(tentative list)
- Andreas Kn?pfer, TU Dresden (chair)
- Denis Barthou, INRIA
- David B?hme, German Research School for Simulation Sciences
- Karl F?rlinger, LMU M?nchen
- Michael Gerndt, TU M?nchen
- Kevin Huck, University of Oregon
- Koji Inoue, Kyushu University
- Ignacio Laguna, Lawrence Livermore National Laboratory
- John Mellor-Crummey, Rice University
- Matthias M?ller, RWTH Aachen University
- Shirley Moore, University of Texas at El Paso
- Martin Schulz, Lawrence Livermore National Laboratory
- Nathan Tallent, Pacific Northwest National Laboratory
- Jan Treibig, RRZE, Friedrich-Alexander-Universit?
- Anh Vo, Microsoft
- Felix Wolf, German Research School for Simulation Sciences
- Brian Wylie, J?lich Supercomputing Centre
Contact
Jos? Gracia
High Performance Computing Center Stuttgart (HLRS)
University of Stuttgart
Email gracia@hlrs.de
--
Dr. Jose Gracia email: gracia@hlrs.de
HLRS, Uni Stuttgart http://www.hlrs.de/people/
Nobelstrasse 19 phone: +49 711 685 87208
70569 Stuttgart fax: +49 711 685 65832
Germany pgp key ID: FBDADD6F
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