[Apologies if you got multiple copies of this email. This message is
sent to . If you'd like to opt out of these
announcements, information on how to unsubscribe is available at the
bottom of this email.]
Sixth International Workshop on
Data Flow Models for Extreme-Scale Computing (DFM 2016)
September 15, Haifa, Israel
http://www.cs.ucy.ac.CY/dfmwor
CALL FOR PAPERS:
The International workshop on "Data-Flow Models (DFM) for extreme scale computing" was held in six consecutive years in conjunction with the PACT conference. The purpose of DFM continues being to bring together those researchers interested in novel computational models based on Data-Flow principles of execution. The switch to multi-core systems has raised concurrency to the level of a major issue if we are to use the increasing number of cores in a chip.
In the past five decades, sequential computing dominated the computer architecture landscape because designers were successful at building faster and faster computers by solely relying on improvements on fabrication technologies and architectural/organization optimizations. The most severe limitation of the sequential model, namely its inability to tolerate long memory latencies has slowed down the performance gains. This phenomenon is the ubiquitous Memory Wall. While various mechanisms have been implemented to overcome the wall (such as extremely efficient hardware prefetch support for example), they only add to another wall that hampers highly efficient execution of programs and modern chip design: the Power Wall. Power considerations and heat dissipation issues have forced manufacturers to switch to multiple cores per chip and thus move into the concurrency era.
New concurrent models/paradigms are needed in order to fully utilize the potential of multi-core chips. The data-flow model is a formal model that can handle concurrency and tolerate memory and synchronization latencies. Data-Flow inspired systems could also be simpler and more power efficient than conventional systems.
Recent work has shown that the data-flow principles can be used to develop systems that can outperform systems based on conventional techniques. Thus, it is time to revisit data-driven computation and bring it to the multi-core and extreme scale computing.
DFM 2016 solicits novel papers that include but are not limited to:
- Novel Data-Flow inspired Execution models and architectures
- Functional and Single assignment based Languages.
- Strict and non-strict execution models.
- Compilers and tools for Data-Flow/Data-Driven systems.
- Hybrid Data-driven/Control-driven systems.
- Position Papers on the Future of Data-Flow in the Multi-core era and beyond.
- All accepted papers will appear in the Computer Society Digital Library
IMPORTANT DATES:
Submission date: July 24, 2016
Authors notification: August 28, 2016
SUBMISSION INFORMATION:
DFM 2015 will accept both Full (8 pages) and Short papers (4 pages). Papers should be prepared using the IEEE Proceedings format; Short Papers could be submitted in the form of extended abstracts. All accepted papers will appear in the Computer Society Digital Library. Submission site https://easychair.org/conferen
PROGRAM COMMITTEE:
Stéphane Zuckerman Co-chair, Univ. of Delaware
Skevos Evripidou Co-chair, University of Cyprus
Guang Gao, University of Delaware
Jean-Luc Gaudiot, University of California at Irvine
Vivek Sarkar, Rice University
Ian Watson, University of Manchester
Kei Hiraki, University of Tokyo
David Abramson, Monash University
Costas Kyriacou, Frederic University
Pedro Trancoso, University of Cyprus
Kyriacos Stavrou, Intel Labs Barcelona, SP
John Feo, Pacific Northwest National Laboratory
Bob Iannucci, CMU, Silicon Valley, USA
Wallid Najjar, University of California, Riverside
Wolfgang Karl, Karlsruhe Institute of Technology
Mark Oskin, University of Washington
Andrew Sohn, NJIT, USA
Reiner Hartenstein, TU Kaiserslautern
Kemal Ebcioğlu, ,Global Supercomputing Corp.Sienna
Kevin Hammond, University of St Andrews
Roberto Giorgi, University of Sienna
Robert Clay, Sandia National Labs
Sven-Bodo Scholz, Heriot-Watt University
Krisha Kavi, Univerity Of North Texas
Yong Meng Teo, National Univ. of Singapore
STEERING COMMITTEE:
Skevos Evripidou, University of Cyprus
Guang Gao, University of Delaware
Jean-Luc Gaudiot, University of California at Irvine
Ian Watson, University of Manchester
Kei Hiraki, University of Tokyo
PUBLICITY CHAIR:
Giorgos Matheou, University of Cyprus
PROCEEDINGS CHAIR:
Costas Kyriacou, Frederic University Cyprus
--
Stéphane Zuckerman
Computer Architecture & Parallel Systems Laboratory
University of Delaware — 201G Evans Hall, Newark, DE
Work #: +1 302 831-6534 Cell #: +1 302 883-9979
******************************
(https://lists.mcs.anl.gov/
If you do not remember your password (which is needed to change these options), you can reset it using the "Unsubscribe or Edit Options" button at the bottom of the page.
(https://lists.mcs.anl.gov/
******************************
sent to . If you'd like to opt out of these
announcements, information on how to unsubscribe is available at the
bottom of this email.]
Sixth International Workshop on
Data Flow Models for Extreme-Scale Computing (DFM 2016)
September 15, Haifa, Israel
http://www.cs.ucy.ac.CY/dfmwor
CALL FOR PAPERS:
The International workshop on "Data-Flow Models (DFM) for extreme scale computing" was held in six consecutive years in conjunction with the PACT conference. The purpose of DFM continues being to bring together those researchers interested in novel computational models based on Data-Flow principles of execution. The switch to multi-core systems has raised concurrency to the level of a major issue if we are to use the increasing number of cores in a chip.
In the past five decades, sequential computing dominated the computer architecture landscape because designers were successful at building faster and faster computers by solely relying on improvements on fabrication technologies and architectural/organization optimizations. The most severe limitation of the sequential model, namely its inability to tolerate long memory latencies has slowed down the performance gains. This phenomenon is the ubiquitous Memory Wall. While various mechanisms have been implemented to overcome the wall (such as extremely efficient hardware prefetch support for example), they only add to another wall that hampers highly efficient execution of programs and modern chip design: the Power Wall. Power considerations and heat dissipation issues have forced manufacturers to switch to multiple cores per chip and thus move into the concurrency era.
New concurrent models/paradigms are needed in order to fully utilize the potential of multi-core chips. The data-flow model is a formal model that can handle concurrency and tolerate memory and synchronization latencies. Data-Flow inspired systems could also be simpler and more power efficient than conventional systems.
Recent work has shown that the data-flow principles can be used to develop systems that can outperform systems based on conventional techniques. Thus, it is time to revisit data-driven computation and bring it to the multi-core and extreme scale computing.
DFM 2016 solicits novel papers that include but are not limited to:
- Novel Data-Flow inspired Execution models and architectures
- Functional and Single assignment based Languages.
- Strict and non-strict execution models.
- Compilers and tools for Data-Flow/Data-Driven systems.
- Hybrid Data-driven/Control-driven systems.
- Position Papers on the Future of Data-Flow in the Multi-core era and beyond.
- All accepted papers will appear in the Computer Society Digital Library
IMPORTANT DATES:
Submission date: July 24, 2016
Authors notification: August 28, 2016
SUBMISSION INFORMATION:
DFM 2015 will accept both Full (8 pages) and Short papers (4 pages). Papers should be prepared using the IEEE Proceedings format; Short Papers could be submitted in the form of extended abstracts. All accepted papers will appear in the Computer Society Digital Library. Submission site https://easychair.org/conferen
PROGRAM COMMITTEE:
Stéphane Zuckerman Co-chair, Univ. of Delaware
Skevos Evripidou Co-chair, University of Cyprus
Guang Gao, University of Delaware
Jean-Luc Gaudiot, University of California at Irvine
Vivek Sarkar, Rice University
Ian Watson, University of Manchester
Kei Hiraki, University of Tokyo
David Abramson, Monash University
Costas Kyriacou, Frederic University
Pedro Trancoso, University of Cyprus
Kyriacos Stavrou, Intel Labs Barcelona, SP
John Feo, Pacific Northwest National Laboratory
Bob Iannucci, CMU, Silicon Valley, USA
Wallid Najjar, University of California, Riverside
Wolfgang Karl, Karlsruhe Institute of Technology
Mark Oskin, University of Washington
Andrew Sohn, NJIT, USA
Reiner Hartenstein, TU Kaiserslautern
Kemal Ebcioğlu, ,Global Supercomputing Corp.Sienna
Kevin Hammond, University of St Andrews
Roberto Giorgi, University of Sienna
Robert Clay, Sandia National Labs
Sven-Bodo Scholz, Heriot-Watt University
Krisha Kavi, Univerity Of North Texas
Yong Meng Teo, National Univ. of Singapore
STEERING COMMITTEE:
Skevos Evripidou, University of Cyprus
Guang Gao, University of Delaware
Jean-Luc Gaudiot, University of California at Irvine
Ian Watson, University of Manchester
Kei Hiraki, University of Tokyo
PUBLICITY CHAIR:
Giorgos Matheou, University of Cyprus
PROCEEDINGS CHAIR:
Costas Kyriacou, Frederic University Cyprus
--
Stéphane Zuckerman
Computer Architecture & Parallel Systems Laboratory
University of Delaware — 201G Evans Hall, Newark, DE
Work #: +1 302 831-6534 Cell #: +1 302 883-9979
******************************
(https://lists.mcs.anl.gov/
If you do not remember your password (which is needed to change these options), you can reset it using the "Unsubscribe or Edit Options" button at the bottom of the page.
(https://lists.mcs.anl.gov/
******************************
No comments:
Post a Comment