Friday 30 August 2013

CALL FOR PAPERS HiPEAC1st International Workshop on Exploiting Silicon Photonics for energy-efficient heterogeneous parallel architectures (SiPhotonics'2014)

CALL FOR PAPERS

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HiPEAC1st International Workshop on Exploiting Silicon Photonics for

energy-efficient heterogeneous parallel architectures (SiPhotonics'2014)
_http://www.hipeac.net/conference/vienna/workshop/siphotonics/2014_

in Vienna, Austria, 21 January 2014

associated with the 9th HiPEAC conference on High Performance and
Embedded Architecture and Compilers
(_http://www.hipeac.net/conference/vienna_).

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*Goal of the Workshop:*

The main purpose of this workshop is to promote further research
interests and activities on Silicon Photonics and related topics in the
perspective of its adoption in future computer systems. In fact Silicon
Photonics poses in itself crucial challenges and interesting design
tradeoffs for being deployed in future computer systems effectively,
also in integration with other technologies. Furthermore, the unique
features of photonics (e.g. extreme low-latency, end-to-end
transmission, high bandwidth density) have the potential to constitute a
/discontinuity /element able to modify the expected /shape/ of future
computer systems from the design point of view and also from the
programmability and/or runtime management perspectives.

Summarizing, silicon photonics can bring innovations and benefits into
current and foreseeable computing systems /directly/, due to their
intrinsic features, but also /indirectly/ enabling the evolution towards
architectures, runtime and resource management approaches that maximize
the photonic raw technologicalopportunities and lead to more efficient
overall designs, otherwise impossible.

This workshop aims to increase the synergy from a complete range of
perspectives, from raw technology issues and solutions up to studies at
the overall system level of modern multi-/many-core systems, both from
academic and industrial researchers working in this area. We are
interested in experimental, systems-related, and work-in-progress papers
in all aspects of the Silicon Photonics technology at all levels of
development.

*Topics of interest:*

The topics of interest include, but are not limited to:

- Integration of positive features of both electronic and photonic
interconnection technology.

- Low-level technological improvements and implications (e.g. integrated
lasers, modulation and detection technologies, microring resonators).

- Fabrication issues (e.g. precision) and new tools (e.g. design, place
and route, ecc) to easy the topological exploration.

- Emerging challenges and solutions for on-chip interconnections, cache
coherence protocols, runtime and OS scheduling, and programmability, for
future homogeneous/heterogeneous energy-aware CMPs

- Simulation, validation and verification

- Photonics in the memory hierarchy and I/O of computing systems

- QoS management and performance analysis

- Programming languages and compilers for thermal-, energy-, and
power-aware architectures

- Solving the requirements of multiple heterogeneous parallel applications.

- Interaction between photonic features and current computer design issues.

- Industrial practices and case studies

*Submission guidelines:*

Prospective authors should submit electronically a full paper in English
in PDF format. Submitted papers must represent original unpublished
research that is not currently under review for any other conference or
journal.

All manuscripts will be reviewed and will be judged on correctness,
originality, technical strength, significance, quality of presentation,
and interest and relevance to the workshop attendees.

They should be formatted according to double-column ACM format pages,
including figures and references. Please use the following template when
preparing your manuscript:
http://www.acm.org/sigs/publications/proceedings-templates,not exceeding
6 pages.

Submissions can be made through the submission web site at

https://www.easychair.org/conferences/?conf=siphotonics2014

*Publication:*

Informal proceedings will be provided in an USB stick to all
participants including all material relevant to the conference and the
related events.

To confirm the publication, at least one author of each accepted paper
is expected to register for the workshop and present the papers at the
workshop itself.

After the conference, authors of selected papers will be invited to
submit an extended version of their contribution for a special issue of
the journal "Concurrency and Computation: Practice and Experience" from
Wiley, scheduled to be published for June 2014.

*Important dates:*

*IMPORTANT DATES*

Title+Abstract deadline (*not mandatory*):     October 31, 2013
Extended paper submission deadline:    November 7, 2013
Notification of acceptance:   December 2, 2013
Camera ready papers due: December 13, 2013
Workshop: Jan 21, 2014
*Co-chairs:*

Jos? M. Garc?a, University of Murcia, Spain.

Sandro Bartolini, University of Siena, Italy

*Program committee:*

KerenBergmanColumbia University

Giovanna Calo'Politecnico di Bari

Jos? M.CeciliaCatholic University of Murcia

YawenChenOtago University

SylvainCollangeINRIA/IRISA

RicardoFern?ndez-PascualUniversity of Murcia

PaoloGraniUniversity of Siena

TimothyJonesUniversity of Cambridge

WolfgangKarlKarlsruhe Institute of Technology (KIT)

KostasKatrinisIBM

S?bastienLe BeuxLyon Institute of Nanotechnology (INL)

OliverMattesKarlsruhe Institute of Technology (KIT)

GokhanMemikNorthwestern University

LasseNatvigNorwegian University of Science and Technology

SudeepPasrichaColorado State University

LucaRaminiUniversity of Ferrara

LaurentScharesIBM TJ Watson

*Contacts:*

Prof. Jos? M. Garc?a

Departamento de Ingenier?a y Tecnolog?a de Computadores

University of Murcia, Spain.

email: jmgarcia[at]ditec.um.es

Tel.: +34 868 884819Fax: +34 868 884151

Ing. Sandro Bartolini, PhD

Dipartimento di Ingegneria dell'Informazione e Scienze Matematiche

University of Siena, Italy

E-mail: bartolini[at]dii.unisi.it

Tel: +39 0577 234850Fax: +39 0577 233609

--
-----------------------------
Prof. Jose Manuel Garcia Carrasco
Departamento de Ingenieria y Tecnologia de Computadores
Facultad de Informatica. Universidad de Murcia
Campus de Espinardo - 30080 Murcia (SPAIN)
Tel.: +34-868-884819    Fax: +34-868-884151
email: jmgarcia@ditec.um.es  |  jm.garcia@ieee.org
url: http://webs.um.es/jmgarcia

Thursday 29 August 2013

WHPCF'13: Sixth Workshop on High Performance Computational Finance

WHPCF'13: Sixth Workshop on High Performance Computational Finance




http://ewh.ieee.org/conf/whpcf
 Monday, November 18th, 2013
 Denver Convention Center
 Denver, Colorado
 Held in conjunction with SC13







Call for Participation:
We cordially invite you to submit a paper to WHPCF'13: Sixth Workshop on
High Performance Computational Finance which is being co-ordinated with
SigHPC. The workshop will be held in conjunction with SC13, the
International Conference for High Performance Computing, Networking,
Storage and Analysis in Denver.

Recent years have seen the dramatic increase in compute capabilities
across a variety of systems. The systems have also become more complex
with trends towards heterogeneous systems consisting of general-purpose
cores and acceleration devices.

The purpose of this workshop is to bring together practitioners,
researchers, vendors, and scholars from the complementary fields of
computational finance and high performance computing, in order to promote
an exchange of ideas, discuss future collaborations and develop new
research directions. Financial companies increasingly rely on high
performance computers to analyze high volumes of financial data,
automatically execute trades, and manage risk.

As financial market data continues to grow in volume and complexity,
computational capabilities of emerging hardware also increases. Extracting
high performance from emerging architectures requires a
combination of domain knowledge and specialized technical skills. The
workshop will explore how researchers, scholars, vendors and practitioners
are collaborating to address high performance computing research
challenges.

We seek submissions that cover various aspects of computational finance.
In addition to submissions that deal with performance and programmability
challenges, theoretical analysis, algorithms, and practical experience in
computational finance, we also particularly encourage submissions that
demonstrate or result from the collaboration between financial
practitioners, and scholars, researchers, or vendors. Topics of interest
to this workshop include, but are not restricted to:

* Financial libraries and run-times
* Use of hardware accelerators (FPGA, Cell, GPUs) in computational finance
* Use of heterogeneous hardware in computational finance
* Financial applications of high performance computing: risk
algorithms, derivative pricing, algorithmic trading, arbitrage
* High-bandwidth/low-latency streaming of market data
* Cluster computing for computational finance
* Financial data center engineering
* Computational algorithms for finance
* Move from capacity to capability computing in financial applications

Submitted papers must be no more than 8 pages in length. Authors are
encouraged to use the ACM two column format. Further instructions for
authors are provided on the workshop webpage. Each submission will receive
at least three reviews from the technical program committee and authors of
selected submissions will have 30 minutes to present their work at the
workshop. Papers should be submitted in electronic form to
dmdaly@us.ibm.com.

Important dates
* Revised submission deadline: 11:59pm EST,  September 2nd
* Author notification: September 30th
* Final version due: October 8th

Organizers
Matthew Dixon (HedgeFacts and the University of San Francisco), David Daly
and Jose Moreira (IBM Thomas J. Watson Research Center)

Program Committee
* Michael Aichinger, RICAM, Austrian Academy of Sciences
* John Ashley, NVIDIA Corporation
* Andreas Binder, MathConsult GmbH
* David Cohen, EMC
* Mike Giles, Oxford University
* Peter Lankford, STAC Research
* Pat Miller, Jump Trading
* Cornelis Oosterlee, TU Delft
* Andrew Rau-Chaplin, Dalhousie University
* Mikhail Smelyanskiy, Intel Corporation
* Mohammed Zubair, Old Dominion University



Jos? E. Moreira
Research Staff Member
Future POWER Systems Concept Team
IBM Thomas J. Watson Research Center
Yorktown Heights NY 10598-0218
phone: 1-914-945-1709, fax: 1-914-945-4425
e-mail: jmoreira@us.ibm.com
URL: http://www.research.ibm.com/people/m/moreira

Wednesday 28 August 2013

CUDA: WEEK IN REVIEW

CUDA Pro Tip: The NVIDIA System Management Interface, or nvidia-smi, is a command-line interface to the NVIDIA Management Library, NVML. nvidia-smi provides Linux system administrators with powerful GPU configuration and monitoring tools. Watch the new CUDACast about nvidia-smi.

Tuesday 27 August 2013

CALL FOR PAPERS: 1st Int. Workshop on High-Performance Stencil Computations (HiStencils 2014)

CALL FOR PAPERS:
1st Int. Workshop on High-Performance
Stencil Computations (HiStencils 2014)
http://www.exastencils.org/histencils
Vienna, Austria, January 21, 2014

in conjunction with HiPEAC 2014 (Jan 20-22, 2014)

======================================
IMPORTANT DATES:
Submission deadline: October  25, 2013
Author notification: November 29, 2013
Final version due:   December 15, 2013
======================================

OVERVIEW:
Stencil computations are an important class of codes used in a variety
of application domains ranging from image and video processing to
simulation and computational science applied in several areas of
natural science. With consumer devices and high-end systems becoming
increasingly powerful, stencil computations are playing an
increasingly important role in research and in applications
alike. Today, real-world stencil codes are often hand-tuned which
requires a huge amount of engineering effort given the variety of
stencil codes in use. Therefore, simplifying the task of constructing
stencil codes that deliver high performance has become an important
topic in research.

HiStencils is a workshop focusing on stencil computations from
embedded environments to exascale computing and advanced software
technology needed to simplify the construction of stencils codes
delivering high performance. HiStencils is intended to bring together
researchers, students and practitioners dealing with, among others,
performance optimzation, code generation and software technology for
stencil computations. We strongly encourage submissions describing
preliminary results, new ideas, position papers, experience reports,
and available tools, with an aim to stimulate discussions,
collaborations, and advances in the field.

Topics of interest include, but are not limited to:
- performance optimization of stencil computations
- auto-tuning and machine learning for stencil codes
- software technology for stencil computations
- stencil code generation for GPUs, accelerators and distributed systems
- stencil applications in embedded systems
- hardware/high-level synthesis for stencil codes
- harnessing stencil computations for exascale performance
- static analysis and verification of stencil codes
- theoretical aspects of stencil computations
- multigrid stencil methods
- tool demonstration


SUBMISSION:

Submissions should not exceed 8 pages (recommended 6 pages) formatted
as per ACM proceedings format. Please use the "tighter alternate
style" (option 2) available from
http://www.acm.org/sigs/publications/proceedings-templates

Submissions should be in PDF format and printable on US Letter or A4
sized paper. Proceedings will be published online and distributed to
the participants. Publication at HiStencils will not prevent later
publication in conferences or journals of the presented work. Please
send your submission by the deadline to:
   histencils@exastencils.org

Post-Proceedings Special Issue:
Selected submissions will be invited for a special issue of
"Parallel Processing Letters" (ISSN 0129-6264) after the workshop.


COMMITTEES:

Organizers and Program Chairs:
Armin Groesslinger (University of Passau, DE)
Harald Koestler (University of Erlangen-Nuremberg, DE)
Contact: histencils@exastencils.org

Program Committee (confirmed members):
Sven Apel (University of Passau, DE)
Matthias Bolten (University of Wuppertal, DE)
Francisco Gaspar (Universidad de Zaragoza, ES)
Dominik Goeddeke (TU Dortmund, DE)
Frank Hannig (University of Erlangen-Nuremberg, DE)
Paul Kelly (Imperial College London, UK)
Hatem Ltaief (KAUST, SA)
Olaf Schenk (Universita della Svizzera Italiana, CH)
Jan Treibig (University of Erlangen-Nuremberg, DE)

Monday 26 August 2013

final release of NVIDIA® Nsight™ Visual Studio Edition 3.1

The NVIDIA Developer Tools team is proud to announce the final release of NVIDIA® Nsight™ Visual Studio Edition 3.1, an application development platform for heterogeneous systems. This new release officially supports Visual Studio 2012Direct3D 11.1, (OpenGL) bindless graphics and CUDA® 5.5.

Please note that this release of Nsight™ Visual Studio Edition requires NVIDIA Display Driver Release 319 or newer.

Download and learn more at Nsight™ Visual Studio Edition Downloads (Sign up and loginrequired).
  • Visual Studio 2012 is now supported.
  • Direct3D 11.1 is now supported.
  • Official support for Microsoft Windows 8 operating system.
  • Support for CUDA 5.5 Toolkit.
  • Support for Direct State Access (DSA) feature of OpenGL.
  • Frame Debugging for (OpenGL) bindless graphics is now supported.
  • Improved Frame Debugger’s event view and performance overhead improvements when tracing DirectX or OpenGL applications.
Beginning with this version, the standalone Nsight™ Visual Studio Edition installer will no longer bundle the CUDA Toolkit. Please obtain the latest version of CUDA 5.5 (available athttp://www.nvidia.com/getcuda) prior to installing Nsight™ Visual Studio Edition if you are using the compute feature set.

We encourage all users to send feedback and report issues at the Nsight™ Visual Studio Edition forums or within the Nsight™ Visual Studio Edition Registered Developer Program to help improve the quality of the software for future releases.

The First announcement and CFPs of HET-NETs 2013 Conference (incl. NET-PEN PhD Course), scheduled for 11 - 13 November 2013, England, UK

Extended Closing Dates

*          Mon 14th of Oct. 2013: Submission of Papers (up to six A4 pages), Works-in-Progress (up to two A4 pages) and Posters (a single A4 page) for peer review;

*          Sat 19th of Oct. 2013: Confirmation of Acceptance / Rejection;

*          Friday 25th of Oct. 2013: Camera Ready Papers (up to ten A4 pages), Works-in-Progress (up to six A4 pages) and Posters (up to four A4 pages).

The First announcement and CFPs of HET-NETs 2013 Conference (incl. NET-PEN PhD Course), scheduled for 11 - 13 November 2013, England, UK
has not taken place as yet due to unexpected organisational issues that took some time to overcome.

We shall be grateful if you would kindly exercise your discretion  and send our announcement and CFP as soon as it is feasible.

Many thanks in anticipation.

Yours sincerely,

Miss Guzlan Miskeen,

HET-NETs 2013 Local Committee


Seventh International Open Conference HET-NETs 2013 (IFIP)
'Performance and Security Modelling & Evaluation of
Cooperative Heterogeneous Networks'
 hpc-announce@mcs.anl.govand
First EU PhD Course NET-PEN 2013
 'Networks and Performance Engineering'

http://www.hetnets2013.eu/

Mon 11th - Wed 13th Nov. 2013
Venue: Craiglands Hotel, Ilkley, West Yorkshire, England, UK

General Chair: Demetres D Kouvatsos (University of Bradford, UK)
PC Co-Chairs: Simonetta Balsamo (University of Ca' Foscari of Venetia, Italy)
                                                                                                                                                                                 Yutaka Takahashi (Kyoto University, Japan)

 First Announcement and CFPs


The Seventh Int. HET-NET 2013 Open Conference is organised under the auspices of the International Federation of Information Processing (IFIP - Event 02691) and aims to (i) Motivate fundamental theoretical and applied research into the modelling, analysis & engineering of performance vs. security trade-offs of evolving, cooperative and converging multi-service networks of diverse technology and the future generation Internet (FGI) and (ii) Provide the appropriate framework for the staging of the First EU PhD course 'NET-PEN 2013', based on selected HET-NETs 2013 technical papers and tutorials.  Contributions are encouraged on, but are not limited to, the following technical themes:
*       Network Traffic Modelling, Characterisation and Engineering
*       Experimental Performance Validation and Measurement Platforms
*       Network Modelling and Analysis of Performance vs. Security Trade-offs
*       Energy-Aware Security and QoS Routing Trade-offs in Wireless Networks
*       Queueing Theoretic-based Models for Intrusion Detection and Elimination Systems
*       CRNs with Dynamic Spectrum Access and Cloud Supporting Platforms
*       Network Security Management Models for Quantum Key Distributions
*       QoS Protocols for Vehicular (VANETs) vs. Robotic (RANETs) Ad Hoc Networks
*       Numerical, Simulation and Analytic Methodologies and Quantitative Tools
*       Queueing Network Models (QNMs) and Gen. Stochastic Petri Nets (GSPNs) with Blocking
*       Optimal Group Network Communication (Broadcasting /Multicasting) Schemes
*       Performance vs. Security  Modelling Issues in Optical Networks
*       Performance Evaluation and Mobility Management in Wireless Networks
*       Modelling and Quantitative Analysis of Overlay Networks
*       End-to-End Quality of Service (QoS) in Cooperative Heterogeneous Networks
*       Quality Feedback for Perceived Service Dependability

                                                                                                                            Important Dates


>  Mon 7th Oct. 2013: Papers (up to six A4 size pages), Works-in-Progress (up to two A4 size pages) and Posters (a single A4 size page) for peer review;

>  Fri 11th Oct. 2013: Confirmation of Acceptance Rejection;

>  Fri 18th Oct. 2013: Camera Ready Papers (up to ten A4 size pages), Works-in-Progress (up to six A4 size pages) and Posters (up to four A4 size pages);

Sunday 25 August 2013

Intel True Scale Fabric Architecture for Enhanced HPC Performance



Intel True Scale Fabric Architecture for Enhanced HPC Performance

Improved interconnect operability increases scalable performance for today’s HPC clusters

There are two types of InfiniBand architectures available today in the marketplace, the first being the traditional InfiniBand design, created as a channel interconnect for the data center. The latest InfiniBand architecture was built with HPC in mind. This enhanced HPC fabric offering is optimized for key interconnect performance factors, featuring MPI message rating, end-to-end latency and collective performance, resulting in increased HPC application performance. Enhanced Intel True Scale Fabric Architecture – Offers 3x to 17x the MPI (Message Passing Interface) message throughput of the other InfiniBand architecture. For many MPI applications, small message rate throughput is an important factor that contributes to overall performance and scalability.

Intel tested a number of MPI applications and found that they performed up to 11 percent better on the cluster based Intel True Scale Fabric QDR-40 (dual-channel) than the traditional InfiniBand-based architecture running at FDR (56 Gbps)
 




  1. Improved end-to-end Latency – End-to-end latency is another key determinant of an MPI application’s performance and ability to scale. The Intel True Scale Fabric end-to-end latency is 50 percent to 90 percent lower at 16 nodes than the traditional InfiniBand offering available today.
  2. Increased Collective Performance – Critical for an MPI application’s performance and ability to scale. Intel True Scale architecture makes it possible to achieve significant collective performance at scale, without hardware based collective acceleration, resulting in 30 percent to 80 percent better collective performance for the three major collectives: All reduce, Barrier, and Broadcast.
  3. Faster Application Performance – Intel tested a number of MPI applications and found that they performed up to 11 percent better on the cluster based Intel True Scale Fabric QDR-40 than the traditional InfiniBand-based architecture running at FDR (56 Gbps).

Conclusion
The interconnect architecture has a cluster and the applications running on the cluster. Intel True Scale Fabric host and switch technologies provide an interconnect infrastructure that maximizes an HPC cluster’s overall performance. The Intel True Scale Fabric Architecture, with its onload protocol processing engine, connectionless implementation, and lightweight semantic-based PSM interface, provides an optimized environment that maximizes MPI application performance. With the use and size of HPC clusters expanding at a rapid architecture and technology extracts the most out of your investment in compute resources by eliminating adapter and switch bottlenecks.

Read the full report :https://www.dropbox.com/s/7tygtfrup0eau7r/Intel-TrueScale_WP_CompleteArchitecturewithPSM.pdf