Wednesday 30 December 2015

Workshop at ISC 2016: Performance Portable Programming Models for Accelerators (P^3MA)

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First International Workshop on Performance Portable Programming Models for Accelerators (P^3MA) http://www.csm.ornl.gov/workshops/p3ma2016/
June 23, 2016 
co-located with ISC 2016 <http://www.isc-hpc.com/home.html>  
June 19 - 23, Frankfurt, Germany
CALL FOR PAPERS
High-Level programming models offer scientific applications a path onto HPC platforms without an undue loss of portability or programmer productivity. For example, using directives, application developers can port their codes to accelerators incrementally while minimizing code changes. Other approaches include Domain Specific Languages, C++ metaprogramming, and runtimes APIs being developed for Exascale which are starting to emerge. Although these approaches aim to introduce abstraction without performance penalty, programming challenges are still manyfold especially with their designs, implementations and application porting experiences on rapidly evolving hardware, some with diverse memory subsystems.
The programming approaches will need to adapt to such developments and make improvements to raise their performance portability that will increase the productivity of accelerators as HPC components. Such improvements are continuously being discussed with standards committees for C++, OpenCL, OpenMP, OpenACC, and Exascale co- design centers for DSLs. This workshop is designed to assess the improved features of programming models (including but not limited to directives-based programming models), their implementations, and experiences with their deployment in HPC applications on multiple architectures.
The workshop will provide a forum for bringing together researchers, vendors, users and developers to brainstorm aspects of heterogeneous computing and its various tools and techniques.
Topics of interest  (but are not limited to):
  • Experience porting applications using high-level models
  • Hybrid heterogeneous or many-core programming with other models such as threading, message passing, and PGAS
  • Performance-portable scientific libraries for heterogeneous systems
  • Experiences in implementing compilers for programming directives on current and emerging architectures
  • Low level communications APIs or runtimes that support accelerator directives
  • Asynchronous task and event driven execution/scheduling
  • Extensions to programming models needed to support multiple memory hierarchies and accelerators
  • Performance modeling and evaluation tools
  • Power/energy studies
  • Auto-tuning or optimization strategies
  • Benchmarks and validation suites

 Important Deadlines:

Abstract Submission: April. 20, 2016 AoE
Full Paper Submission:  April 29th, 2016 AoE
Paper Notification: May. 27, 2016
Camera Ready Paper: June 03, 2016

Review process
Abstracts and papers need to be submitted via Easy Chair : https://easychair.org/conferences/?conf=p3ma
We only accept paper submissions which are formatted correctly in LNCS style (single column format) using either the LaTeX document class or Word template. For details on the author guidelines, please refer to Springer’s website. Incorrectly formatted papers will be excluded from the reviewing process.
Papers submissions are required to be within 18 pages in the above mentioned LNCS style. This includes all figures and references.
The submissions are "single-blind", i.e. submissions are allowed to include the author names.
All submitted manuscripts will be reviewed. The review process is not double blind, i.e., authors will be known to reviewers. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the conference scope. Submitted papers may NOT have appeared in or be under consideration for another conference, workshop or journal.
ORGANIZATION COMMITTEE
Steering Committee
Matthias Muller, RWTH Aachen University, Germany 
Barbara Chapman, University of Houston, USA 
Oscar Hernandez, ORNL, USA
Duncan Poole, OpenACC, USA
Torsten Hoefler, ETH, Zurich
Michael Wong, OpenMP, Canada
Mitsuhisa Sato, University of Tsukuba, Japan

Program Chair(s)
Sunita Chandrasekaran, University of Delaware, USA <schandra@udel.edu
Graham Lopez, ORNL, USA <lopezmg@ornl.gov>

Program Committee 
Wei Ding, AMD, USA
Michael Klemm, Intel, Germany
Adrian Jackson, EPCC, UK
Andreas Knuepfer, TU Dresden, Germany
Suraj Prabhakaran, TU Darmstadt, Germany
Will Sawyer, CSCS, ETH, Zurich
Amit Amritkar, University of Houston, USA
Sameer Shende, University of Oregon, USA
James Beyer, NVIDIA, USA
Saber Feki, KAUST, Saudi Arabia
Guido Juckeland, TU Dresden, Germany
Costas Bekas, IBM, Zurich
Henri Jin, NASA-Ames, USA
Steven Olivier, Sandia National Lab, USA

Questions?  Please contact one of the program chairs.


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Workshop at ISC 2016: Performance Portable Programming Models for Accelerators (P^3MA)

[Apologies if you got multiple copies of this email. This message is
sent to . If you'd like to opt out of these
announcements, information on how to unsubscribe is available at the
bottom of this email.]

First International Workshop on Performance Portable Programming Models for Accelerators (P^3MA) http://www.csm.ornl.gov/workshops/p3ma2016/
June 23, 2016 
co-located with ISC 2016 <http://www.isc-hpc.com/home.html>  
June 19 - 23, Frankfurt, Germany
CALL FOR PAPERS
High-Level programming models offer scientific applications a path onto HPC platforms without an undue loss of portability or programmer productivity. For example, using directives, application developers can port their codes to accelerators incrementally while minimizing code changes. Other approaches include Domain Specific Languages, C++ metaprogramming, and runtimes APIs being developed for Exascale which are starting to emerge. Although these approaches aim to introduce abstraction without performance penalty, programming challenges are still manyfold especially with their designs, implementations and application porting experiences on rapidly evolving hardware, some with diverse memory subsystems.
The programming approaches will need to adapt to such developments and make improvements to raise their performance portability that will increase the productivity of accelerators as HPC components. Such improvements are continuously being discussed with standards committees for C++, OpenCL, OpenMP, OpenACC, and Exascale co- design centers for DSLs. This workshop is designed to assess the improved features of programming models (including but not limited to directives-based programming models), their implementations, and experiences with their deployment in HPC applications on multiple architectures.
The workshop will provide a forum for bringing together researchers, vendors, users and developers to brainstorm aspects of heterogeneous computing and its various tools and techniques.
Topics of interest  (but are not limited to):
  • Experience porting applications using high-level models
  • Hybrid heterogeneous or many-core programming with other models such as threading, message passing, and PGAS
  • Performance-portable scientific libraries for heterogeneous systems
  • Experiences in implementing compilers for programming directives on current and emerging architectures
  • Low level communications APIs or runtimes that support accelerator directives
  • Asynchronous task and event driven execution/scheduling
  • Extensions to programming models needed to support multiple memory hierarchies and accelerators
  • Performance modeling and evaluation tools
  • Power/energy studies
  • Auto-tuning or optimization strategies
  • Benchmarks and validation suites

 Important Deadlines:

Abstract Submission: April. 20, 2016 AoE
Full Paper Submission:  April 29th, 2016 AoE
Paper Notification: May. 27, 2016
Camera Ready Paper: June 03, 2016

Review process
Abstracts and papers need to be submitted via Easy Chair : https://easychair.org/conferences/?conf=p3ma
We only accept paper submissions which are formatted correctly in LNCS style (single column format) using either the LaTeX document class or Word template. For details on the author guidelines, please refer to Springer’s website. Incorrectly formatted papers will be excluded from the reviewing process.
Papers submissions are required to be within 18 pages in the above mentioned LNCS style. This includes all figures and references.
The submissions are "single-blind", i.e. submissions are allowed to include the author names.
All submitted manuscripts will be reviewed. The review process is not double blind, i.e., authors will be known to reviewers. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the conference scope. Submitted papers may NOT have appeared in or be under consideration for another conference, workshop or journal.
ORGANIZATION COMMITTEE
Steering Committee
Matthias Muller, RWTH Aachen University, Germany 
Barbara Chapman, University of Houston, USA 
Oscar Hernandez, ORNL, USA
Duncan Poole, OpenACC, USA
Torsten Hoefler, ETH, Zurich
Michael Wong, OpenMP, Canada
Mitsuhisa Sato, University of Tsukuba, Japan

Program Chair(s)
Sunita Chandrasekaran, University of Delaware, USA <schandra@udel.edu
Graham Lopez, ORNL, USA <lopezmg@ornl.gov>

Program Committee 
Wei Ding, AMD, USA
Michael Klemm, Intel, Germany
Adrian Jackson, EPCC, UK
Andreas Knuepfer, TU Dresden, Germany
Suraj Prabhakaran, TU Darmstadt, Germany
Will Sawyer, CSCS, ETH, Zurich
Amit Amritkar, University of Houston, USA
Sameer Shende, University of Oregon, USA
James Beyer, NVIDIA, USA
Saber Feki, KAUST, Saudi Arabia
Guido Juckeland, TU Dresden, Germany
Costas Bekas, IBM, Zurich
Henri Jin, NASA-Ames, USA
Steven Olivier, Sandia National Lab, USA

Questions?  Please contact one of the program chairs.


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CFP: BPOE-7 Co-located with ASPLOS 2016

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BPOE-7 Call for Papers
-------------------------
The Seventh workshop on Big Data Benchmarks, Performance Optimization, and Emerging Hardware
Co-located with ASPLOS 2016
April 3rd, 2016, Atlanta, Georiga, USA
* Introduction
Big data has emerged as a strategic property of nations and organizations. There are driving needs to generate values from big data. 
However, the sheer volume of big data requires significant storage capacity, transmission bandwidth, computations, and power consumption. 
It is expected that systems with unprecedented scales can resolve the problems caused by varieties of big data with daunting volumes. 
Nevertheless, without big data benchmarks, it is very difficult for big data owners to make choice on which system is best for meeting 
with their specific requirements. They also face challenges on how to optimize the systems and their solutions for specific or even 
comprehensive workloads. Meanwhile, researchers are also working on innovative data management systems, hardware architectures, operating 
systems, and programming systems to improve performance in dealing with big data.
This workshop, the seventh its series, focuses on architecture and system support for big data systems, aiming at bringing researchers and 
practitioners from data management, architecture, and systems research communities together to discuss the research issues at the intersection 
of these areas.
* Call for papers
Topics:
The workshop seeks papers that address hot topic issues in benchmarking, designing and optimizing big data systems. Specific topics of interest 
include but are not limited to:
** Big data workload characterization and benchmarking
** Performance analysis of big data systems
** Workload-optimized big data systems
** Innovative prototypes of big data infrastructures
** Emerging hardware technologies in big data systems
** Operating systems support for big data systems
** Interactions among architecture, systems and data management
** Hardware and software co-design for big data
** Practice report of evaluating and optimizing large-scale big data systems
Papers should present original research. As big data spans many disciplines, papers should provide sufficient background material to make them 
accessible to the broader community.
* Paper Submissions
Papers must be submitted in PDF, and be no more than 8 pages in standard two-column SIGPLAN conference format including figures and tables but not including references. Shorter submissions are encouraged. The submissions
will be judged based on the merit of the ideas rather than the length. Submissions must be made through the online submission site. The expanded 
version will be published by Springer LNCS (pending).
Best paper award will be announced at the end of the workshop!
* Important dates:
Papers due February 3rd, 2016.
Notification of acceptance February 23, 2016
Camera-ready copies March 30, 2016
Workshop Session April 3rd, 2016
* Program Committee (updated on 2015/3/5)
TBD
* Organization
Steering committee:
** Christos Kozyrakis, Stanford
** Xiaofang Zhou, University of Queensland
** Dhabaleswar K Panda, Ohio State University
** Aoying Zhou, East China Normal University
** Raghunath Nambiar, Cisco
** Lizy K John, University of Texas at Austin
** Xiaoyong Du, Renmin University of China
** Ippokratis Pandis, IBM Almaden Research Center
** Xueqi Cheng, ICT, Chinese Academy of Sciences
** Bill Jia, Facebook
** Lidong Zhou, Microsoft Research Asia
** H. Peter Hofstee, IBM Austin Research Laboratory
** Alexandros Labrinidis, University of Pittsburgh
** Cheng-Zhong Xu, Wayne State University
** Jianfeng Zhan, ICT, Chinese Academy of Sciences
** Guang R. Gao, University of Delaware.
** Yunquan Zhang, ICT, Chinese Academy of Sciences
PC Co-Chair:
Web and Publicity Chairs:
Zhen Jia, ICT, Chinese Academy of Sciences and UCAS
Wanling Gao, ICT, Chinese Academy of Sciences and UCAS
* Previous Events
BPOE-1 October 7,2013 IEEE BigData Conference, San Jose, CA
BPOE-2 October 31,2013 CCF HPC China, Guilin, China
BPOE-3 December 5,2013 CCF Big Data Technology Conference 2013, BeiJing, China
BPOE-4 March 1,2014 ASPLOS 2014, Salt Lake City, Utah, USA
BPOE-5 September 5,2014 VLDB 2014, Hangzhou, Zhejiang Province, China
BPOE-6 September 4,2015 VLDB 2015, Hilton Waikoloa Village, Kohala Coast, Hawai'i

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CFP: BPOE-7 Co-located with ASPLOS 2016

[Apologies if you got multiple copies of this email. This message is
sent to . If you'd like to opt out of these
announcements, information on how to unsubscribe is available at the
bottom of this email.]


BPOE-7 Call for Papers
-------------------------
The Seventh workshop on Big Data Benchmarks, Performance Optimization, and Emerging Hardware
Co-located with ASPLOS 2016
April 3rd, 2016, Atlanta, Georiga, USA
* Introduction
Big data has emerged as a strategic property of nations and organizations. There are driving needs to generate values from big data. 
However, the sheer volume of big data requires significant storage capacity, transmission bandwidth, computations, and power consumption. 
It is expected that systems with unprecedented scales can resolve the problems caused by varieties of big data with daunting volumes. 
Nevertheless, without big data benchmarks, it is very difficult for big data owners to make choice on which system is best for meeting 
with their specific requirements. They also face challenges on how to optimize the systems and their solutions for specific or even 
comprehensive workloads. Meanwhile, researchers are also working on innovative data management systems, hardware architectures, operating 
systems, and programming systems to improve performance in dealing with big data.
This workshop, the seventh its series, focuses on architecture and system support for big data systems, aiming at bringing researchers and 
practitioners from data management, architecture, and systems research communities together to discuss the research issues at the intersection 
of these areas.
* Call for papers
Topics:
The workshop seeks papers that address hot topic issues in benchmarking, designing and optimizing big data systems. Specific topics of interest 
include but are not limited to:
** Big data workload characterization and benchmarking
** Performance analysis of big data systems
** Workload-optimized big data systems
** Innovative prototypes of big data infrastructures
** Emerging hardware technologies in big data systems
** Operating systems support for big data systems
** Interactions among architecture, systems and data management
** Hardware and software co-design for big data
** Practice report of evaluating and optimizing large-scale big data systems
Papers should present original research. As big data spans many disciplines, papers should provide sufficient background material to make them 
accessible to the broader community.
* Paper Submissions
Papers must be submitted in PDF, and be no more than 8 pages in standard two-column SIGPLAN conference format including figures and tables but not including references. Shorter submissions are encouraged. The submissions
will be judged based on the merit of the ideas rather than the length. Submissions must be made through the online submission site. The expanded 
version will be published by Springer LNCS (pending).
Best paper award will be announced at the end of the workshop!
* Important dates:
Papers due February 3rd, 2016.
Notification of acceptance February 23, 2016
Camera-ready copies March 30, 2016
Workshop Session April 3rd, 2016
* Program Committee (updated on 2015/3/5)
TBD
* Organization
Steering committee:
** Christos Kozyrakis, Stanford
** Xiaofang Zhou, University of Queensland
** Dhabaleswar K Panda, Ohio State University
** Aoying Zhou, East China Normal University
** Raghunath Nambiar, Cisco
** Lizy K John, University of Texas at Austin
** Xiaoyong Du, Renmin University of China
** Ippokratis Pandis, IBM Almaden Research Center
** Xueqi Cheng, ICT, Chinese Academy of Sciences
** Bill Jia, Facebook
** Lidong Zhou, Microsoft Research Asia
** H. Peter Hofstee, IBM Austin Research Laboratory
** Alexandros Labrinidis, University of Pittsburgh
** Cheng-Zhong Xu, Wayne State University
** Jianfeng Zhan, ICT, Chinese Academy of Sciences
** Guang R. Gao, University of Delaware.
** Yunquan Zhang, ICT, Chinese Academy of Sciences
PC Co-Chair:
Web and Publicity Chairs:
Zhen Jia, ICT, Chinese Academy of Sciences and UCAS
Wanling Gao, ICT, Chinese Academy of Sciences and UCAS
* Previous Events
BPOE-1 October 7,2013 IEEE BigData Conference, San Jose, CA
BPOE-2 October 31,2013 CCF HPC China, Guilin, China
BPOE-3 December 5,2013 CCF Big Data Technology Conference 2013, BeiJing, China
BPOE-4 March 1,2014 ASPLOS 2014, Salt Lake City, Utah, USA
BPOE-5 September 5,2014 VLDB 2014, Hangzhou, Zhejiang Province, China
BPOE-6 September 4,2015 VLDB 2015, Hilton Waikoloa Village, Kohala Coast, Hawai'i

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Special issue of Scientific Programming on Hardware-Software Codesign for HPC -- deadline January 29

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sent to . If you'd like to opt out of these
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Call for Papers

Hardware-software codesign involves the concurrent design of hardware and software components of complex computer systems, whereby application requirements influence architecture design and hardware constraints influence design of algorithms and software. High Performance Computing (HPC) is facing daunting challenges as we move towards the exascale era, with the necessity of designing systems that run large-scale simulations with high performance while meeting cost and energy consumption constraints. Effective codesign requires collaboration between domain scientists, applied mathematicians, computer scientists, and hardware architects. Representative proxy applications, ranging from kernels to miniapplications, must be extracted from and validated against full applications to allow for evaluation on new and emerging hardware architectures. Hardware must be designed to meet application requirements while meeting cost constraints. Finally, system software must be designed that supports the programming and execution models required for highly concurrent, complex, and heterogeneous applications and systems.
We solicit high quality, original research articles as well as review articles focused on the interrelationships between algorithms/applications, systems software, and hardware and on methodologies and tools for hardware-software codesign for HPC.
Potential topics include, but are not limited to:
  • Use of simulation and emulation techniques for codesign
  • Modeling and prediction of performance and energy consumption
  • Cooptimization for multiple objectives (such as performance, power, and resilience)
  • Evaluation of new processor and memory technologies for scientific applications
  • Mapping of algorithms and applications to heterogeneous systems
  • Concurrent design space exploration of software and hardware
  • Design and validation of proxy applications
  • Bounds analysis of application requirements with respect to data movement and power/energy consumption
  • Programming and execution models for new architectures
  • Design and use of reconfigurable hardware for meeting application requirements
Authors can submit their manuscripts via the Manuscript Tracking System at http://mts.hindawi.com/submit/journals/sp/hhpc/.
Manuscript Due29 January 2016
First Round of ReviewsApril 2016
Publication DateJuly 2016

Lead Guest Editor

Guest Editors


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Special issue of Scientific Programming on Hardware-Software Codesign for HPC -- deadline January 29

[Apologies if you got multiple copies of this email. This message is
sent to . If you'd like to opt out of these
announcements, information on how to unsubscribe is available at the
bottom of this email.]

Call for Papers

Hardware-software codesign involves the concurrent design of hardware and software components of complex computer systems, whereby application requirements influence architecture design and hardware constraints influence design of algorithms and software. High Performance Computing (HPC) is facing daunting challenges as we move towards the exascale era, with the necessity of designing systems that run large-scale simulations with high performance while meeting cost and energy consumption constraints. Effective codesign requires collaboration between domain scientists, applied mathematicians, computer scientists, and hardware architects. Representative proxy applications, ranging from kernels to miniapplications, must be extracted from and validated against full applications to allow for evaluation on new and emerging hardware architectures. Hardware must be designed to meet application requirements while meeting cost constraints. Finally, system software must be designed that supports the programming and execution models required for highly concurrent, complex, and heterogeneous applications and systems.
We solicit high quality, original research articles as well as review articles focused on the interrelationships between algorithms/applications, systems software, and hardware and on methodologies and tools for hardware-software codesign for HPC.
Potential topics include, but are not limited to:
  • Use of simulation and emulation techniques for codesign
  • Modeling and prediction of performance and energy consumption
  • Cooptimization for multiple objectives (such as performance, power, and resilience)
  • Evaluation of new processor and memory technologies for scientific applications
  • Mapping of algorithms and applications to heterogeneous systems
  • Concurrent design space exploration of software and hardware
  • Design and validation of proxy applications
  • Bounds analysis of application requirements with respect to data movement and power/energy consumption
  • Programming and execution models for new architectures
  • Design and use of reconfigurable hardware for meeting application requirements
Authors can submit their manuscripts via the Manuscript Tracking System at http://mts.hindawi.com/submit/journals/sp/hhpc/.
Manuscript Due29 January 2016
First Round of ReviewsApril 2016
Publication DateJuly 2016

Lead Guest Editor

Guest Editors


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Sunday 6 December 2015

19th Euromicro Conference on Digital System Design: first call for papers




19th Euromicro Conference on Digital System Design
Limassol, Cyprus, Aug. 31st - Sept. 2nd, 2016

Conference webpage: http://dsd2016.cs.ucy.ac.cy

                     Call for Papers

SCOPE
The Euromicro Conference on Digital System Design (DSD) addresses all aspects of
(embedded, pervasive and high-performance) digital and mixed HW/SW system engineering,
covering the whole design trajectory from specification down to micro-architectures,
digital circuits and VLSI implementations. It is a forum for researchers and engineers
from academia and industry working on advanced investigations, developments and applications.
It focuses on today’s and future challenges of advanced system architectures for embedded
and high-performance HW/SW systems, application analysis and parallelization,
design automation for all design levels, as well as, on modern implementation technologies
from full custom in nanometer technology nodes, through FPGAs, to multi-core infrastructures.
It covers a multitude of highly relevant design aspects from system, hardware and
embedded-software specification, modeling, analysis, synthesis and validation,
through system adaptability, security, dependability and fault tolerance,
to system energy consumption minimization and multi-objective optimization.
Authors are kindly invited to submit their work according (but not limited)
to the seven main topics of the conference main track. In addition,
eight Special Sessions (with their own coordinators and subprogram committees)
do also welcome contributions in specific themes of particular interest.
All papers are reviewed following guidelines, quality requirements and thresholds
that are common to all committees.


MAIN TOPICS

T1: Advanced applications of embedded and cyber-physical systems
Challenging and highly-demanding modern applications in (wireless) communication and networking;
networked electronic media, multimedia and ambient intelligence; image and video processing;
mobile systems; ubiquitous, wearable and implanted systems; military, space, avionics, measurement,
control and automotive applications; wireless sensor network applications; surveillance and security;
environmental, agriculture, urban, building, transportation, traffic, energy, hazard and disaster monitoring
and control.
T2: Application analysis and parallelization for embedded and high-performance hardware and software design
Application profiling, characterization and bottleneck detection; application restructuring for parallelism;
application parallelization, information-flow analysis, scheduling and mapping for application-specific processor;
MPSoC memory and communication architecture synthesis; HW/SW co-design and algorithm/architecture matching;
combined hardware/software design space exploration and HW/SW system multi-objective optimization; parallelization,
scheduling and mapping of applications for (heterogeneous) processor and MPSoC architectures; re-targetable
(application-specific) compilation; architectural support for compilers/programming models; performance,
energy consumption and other parametric analysis for HW/SW systems; analytical modeling and simulation tools;
benchmark applications, workload and benchmarking for heterogeneous HW/SW systems; virtual and FPGA-based system prototyping.
T3: Specification, modeling, analysis, verification and test for systems, hardware and embedded software
Modeling, simulation, design and verification languages; functional, structural and parametric specification and modeling;
model-based design and verification; system, hardware, and embedded software analysis, simulation, emulation, prototyping,
formal verification, design-for-test and testing at all design levels; dependability, safety, security and fault-tolerance issues.
T4: Design and synthesis of systems, hardware and embedded software
Quality-driven design; model-, platform- and template-based design; design-space exploration; multi-objective optimization;
system, processor, memory and communication architecture design; application scheduling and mapping to platforms;
(Heterogeneous) multiprocessor systems on-a-chip (MPSoC), hardware multiprocessors and complex accelerators; generic system platforms
and platform-based design; processor, memory and communication architectures; 3D MPSoCs and 3D NoCs; ASIP- and GPU-based platforms;
software design and programming models for multicore platforms; IP design, standardization and reuse; parallelism exploitation and scalability techniques; virtual components; system of systems; compiler assisted MPSoCs; hardware support for embedded kernels; embedded software features; static, run-time and dynamic optimizations of embedded MPSoCs; benchmarks and benchmarking for MPSoCs; NoC architecture and quality of service; power dissipation and energy issues in SoCs and NoCs.
T6: Programmable/reconfigurable/adaptable architectures
Design methodologies and tools for reconfigurable computing; run-time, partial and dynamic reconfiguration; fine-grained,
mixed-grained and coarse-grained reconfigurable architectures; reconfigurable interconnections and NoCs; FPGAs;
systems on reconfigurable chip; system FPGAs, structured ASICs; co-processors; processing arrays; programmable fabrics;
adaptive computing devices, systems and software; adaptable ASIPs and ASIP-based MPSoCs; hardware accelerators;
optimization of FPGA-based cores; shared resource management; novel models, design algorithms and tools for FPGAs and
FPGA-based systems; rapid prototyping systems and platforms; adaptable wireless and mobile systems.
T7: New issues introduced by emerging technologies
Important issues for system, circuit and embedded software design introduced by e.g. the nanometer CMOS and beyond CMOS technologies, 3D integration, optical and other new memory and communication technologies; new human-machine interfaces; neural- and bio-computation; (bio)sensor and sensor network technologies; pervasive and ubiquitous computing (Internet of Things); related design methods and EDA tools; Flexible Digital Radio-digital architecture design and methodologies concepts for multi-standard, multi-mode flexible radios.


SPECIAL SESSIONS/ORGANIZERS

DTFT:    Dependability, Testing and Fault Tolerance in Digital Systems – H. Kubatova (CTU Prague, CZ), Z. Kotasek (TU Brno, CZ)
MCSDIA: Mixed Criticality System Design, Implementation and Analysis – K. Gruttner (OFFIS, DE), E. Villar (TEISA U Cantabria, ES)
AHSA:    Architectures and Hardware for Security Applications – Paris Kitsos (TEI of Western Greece, GR)
DCPS:    Design of Heterogeneous Cyber-Physical Systems – M. Geilen, (TUE, NL), D. Quaglia (U Verona, IT)
ASHWPA:    Advanced Systems in Healthcare, Wellness and Personal Assistance – F. Leporati (U Pavia, IT)
ASAIT:     Architectures and Systems for Automotive and Intelligent Transportation – S. Niar (U Valenciennes, FR)
SDSG:    System Design for the Smart Grid – R. Jacobsen (Aarhus U, DK), E. Ebeid (Aarhus U, DK)
EPDSD:    European Projects in Digital System Design – F. Leporati (U Pavia, IT), L. Jozwiak (TUE, NL)


SUBMISSION GUIDELINES

Authors are encouraged to submit their manuscripts to https://easychair.org/conferences/?conf=dsd2016.
Should an unexpected web access problem be encountered, please contact the Program Chair by email
(dsd2016@easychair.org). Each manuscript should include the complete paper text, all illustrations,
and references. The manuscript should conform to the IEEE format: single-spaced, double column,
US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review,
no indication of the authors' names should appear in the manuscript, references included.
CPS, Conference Publishing Services, publishes the (ISI indexed) DSD Proceedings, available worldwide
through the IEEE Xplore Digital Library. Extended versions of selected best papers will be published
in a special issue of the ISI indexed “Microprocessors and Microsystems: Embedded Hardware Design” Elsevier journal.


IMPORTANT DATES

Deadline for paper submission: April 8th, 2016
Notification of acceptance: May 30th, 2016
Camera ready papers: June 27th, 2016


DSD STEERING COMMITTEE
Lech Jozwiak (TU Eindhoven, NL) - Chairman
Krzysztof Kuchcinski (U Lund, SE)
Antonio Nunez (IUMA/ULPGC, ES)
Francesco Leporati (U Pavia, IT)
Eugenio Villar (TEISA U Cantabria, ES)
Jose Silva Matos (U Porto, PT)

PROGRAM CHAIRS
Paris Kitsos (TEI West. Greece, GR) - Chair
Odysseas Koufopavlou (U Patras, GR) - Honorary chair

GENERAL CHAIR
George A. Papadopoulos (U Cyptus, CY)

PUBLICATION CHAIR
A. Skavhaug (Norwegian UST, NO)

PROGRAM COMMITTEE
P. Athanas (Virginia Tech, US)
H. Basson (U. Littoral, FR)
T. Basten (TU Eindhoven, NL)
N. Bergmann (U Queensland, AU)
C. Bouganis (Imp. Coll., UK)
P. Carballo (ULPGC, ES)
T. Chen (Colorado St., US)
G. Danese (U Pavia, IT)
J. Dondo (UCLM,  ES)
R. Drechsler (U Bremen, DE)
L. Fanucci (U Pisa, IT)
J. Ferreira (U Porto, PT)
M. Figueroa (U Concepcion, CL)
K. Gaj (George Mason U, US)
P. Gao (Aries Design, US)
V. Goulart (U Kyushu, JP)
G. Jacquemod (U Nice-Sophia, FR)
J. Haid (Infineon, AT)
I. Hamzaoglu (U Sabanci, TR)
A. Hemani (KTH, SE)
D. Houzet (Grenoble IT, FR)
M. Hubner (RUB, DE)
L. Jozwiak (TU Eindhoven, NL)
B. Juurlink (TU Berlin, DE)
K. Kent (U New Brunswick, CN)
P. Kitsos (TEI of Western Greece, GR)
Z. Kotasek, (TU Brno, CZ)
H. Kubatova (CTU Prague, CZ)
K. Kuchcinski (U Lund, SE)
S. Kumar (U Jonkoping, SE)
A. Kumar (NUS, SG)
A. Lastovetsky (U Coll Dublin, IE)
J. Lee (U Chosun, KR)
F. Leporati (U Pavia, IT)
E. Martins (U Aveiro, PT)
J. Matos (U Porto, PT)
S. Mosin (Vladimir State U, RU)
V. Muthukumar (U Nevada, US)
N. Nedjah (U Rio de Janeiro, BR)
H. Neto (UT Lisboa, PT)
S. Niar (U Valenciennes, FR)
D. Noguet (CEA, FR)
A. Nunez (ULPGC, ES)
A. Pawlak (ITE&SUT, PL)
L. Peng (Louisiana State U, US)
T. Pionteck (U Lubeck, DE)
A. Postula (U Queensland, AU)
Y. Qu (Mediatek, FI)
D. Quaglia (U Verona, IT)
D. Rossi (U Bologna, IT)
J. Sahuquillo (U Pol Valencia, ES)
J. Schmidt (CTU Prague, CZ)
C. Silvano (Pol Milano, IT)
A. Skavhaug (Norwegian UST, NO)
N. Sklavos (U Patras, GR)
L. Sousa (UT Lisboa, PT)
W. Stechele (TU Munich, DE)
A. Tokarnia (U Campinas, BR)
R. Ubar (IT Tallin, EE)
M. Velev (Aries Design, US)
H. Vierhaus (BTU Cottbus, DE)
T. Villa (U Verona, IT)
E. Villar (U Cantabria, ES)
S. Vitabile (U. Palermo, IT)
C. Wang (USTC, CN)
C. Wolinski (IRISA, FR)
A. Yurdakul (U Bogazici, TR)

--
--------------------------------------------------------
Paris Kitsos, Ph.D. Assistant Professor
Digital IC dEsign and Systems Lab (DICES Lab),
Computer & Informatics Engineering Department (CIED),
Technological Educational Institute of Western Greece,
National Road Antirrion - Ioannina, GR-30020, Greece
Telephone: +30 26310 58491 (Direct), +30 26340 38566-67 (Registry)
Fax: +30 26340 29667 (Registry)
E-mails: pkitsos@teimes.gr , pkitsos@ieee.org
Webpage: http://diceslab.cied.teiwest.gr
--------------------------------------------------------


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CFP: The Twelfth IEEE Workshop on High-Performance Power-Aware Computing (HPPAC'16)





                                                      CALL FOR PAPERS:
The Twelfth IEEE Workshop on High-Performance Power-Aware Computing (HPPAC)
                                                   May 27th, 2016, Chicago
Held in conjunction with  IEEE International Parallel & Distributed Processing Symposium (IPDPS)

Power and energy are now recognized as first-order constraints 
in high-performance computing.  Optimizing performance under power
and energy bounds requires coordination across not only the software
stack (compilers, operating and runtime systems, job schedulers) but 
also coordination with cooling systems and outwards to electrical
suppliers.  As we continue to move towards exascale and extreme scale 
computing, understanding how power translates to performance 
becomes an increasingly critical problem.

The purpose of this workshop is to provide a forum where cutting-edge
research in the above topic can be shared with others in the community.
As such, while we welcome full (10 page) papers as in previous years,
we are now also soliciting short papers (4 pages max).  While both should
conform to the list of topics below, short papers will be judged primarily
on their interest to the community.  As such, these may be position papers,
initial results, open problems, software announcements, or interesting
work that does not reach the level of a full-paper treatment.  
All papers will be subject to single-blind peer review, and the quality of
both the short and standard papers is expected to be high.

Topics of particular interest include (but are not limited to):

* Performance optimization across node, job, cluster and site power bounds.
* Power/performance tradeoffs across accelerators, processors and DRAM.
* Cooling/performance tradeoffs.
* Translating budgetary bounds into power and energy bounds.
* Efficient system design, from computer center to silicon
* Effects of compiler optimizations on code power and energy efficiency
* Power- and energy-aware job schedulers, runtime systems and operating systems.
* Models of power and performance, from processors to computer centers.
* Evaluations of hardware power and energy controls

Important dates: 

Full papers (10 pages max):                          
Deadline: Jan. 22nd
Automatic Extension: Jan. 29th
Author notification: Feb. 12th
Camera-ready copy: Feb. 26th

Short papers (4 pages max):
Deadline: Jan. 29th
Automatic Extension: Feb. 5th
Author notification: Feb. 19th
Camera-ready copy: Feb. 26th

All dates are AOE ("Anywhere on earth").

Paper submissions:
Submissions should follow the IEEE Conference Proceedings templates found 
Camera-ready copy will need to conform to IPDPS guidelines; these will be 
announced during author notification.



Workshop Co-Chairs:
Barry Rountree, LLNL  rountree@llnl.gov
Shuaiwen Leon Song, PNNL   shuaiwen.song@pnnl.gov


Program Committee 

Inoue Koji, Kyushu University Fukuoka, Japan
Thomas Ilsche, Technische Universität Dresden, Germany
Torsten Wilde, Leibniz Supercomputing Centre,  Germany
Peter Bailey, Google, USA
Lizhong Chen, Oregon State University, USA
Frank Mueller, North Carolina State University, USA
Aniruddha Marathe, Lawrence Livermore National Lab, USA
Joseph Greathouse, AMD, USA
Suzanne Rivoire, Sonoma State University, USA
Natalie Bates, Energy Efficient HPC Working Group, USA
Michael Bader, Technische Universitat Munchen, Germany
Shirley Moore, University of Texas at El Paso, USA
Kirk Cameron, Virginia Tech, USA 
Kevin Barker, Pacific Northwest National Lab, USA





Shuaiwen Leon Song
Staff Research Scientist 
High Performance Computing Group,
Advanced Computing, Mathematics, and Data Division,
Pacific Northwest National Lab (PNNL), 
Washington, US,
Office:509-372-4189

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
It is never too late to become what you might have been.       ^
-- George Elliot                                                                    ^
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^


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