Network-on-Chip
(DRNoC 2013)
*CALL FOR PAPERS*
As part of
The International Conference on High Performance Computing & Simulation
(HPCS 2013)
http://hpcs2013.cisedu.info/
July 1st ? July 5th 2013
Helsinki, Finland
*Submissions could be for full papers, short papers, or poster papers*
*IMPORTANT DATES*
Paper Submissions: ------------------------------
Acceptance Notification: ------------------------------
Camera Ready Papers and Registration Due: ---April 18, 2013
Conference Dates: ------------------------------
*
SCOPE AND OBJECTIVES*
Network-on-chip (NoC) has been recently proposed for SoC applications
design to achieve better performance and lower energy consumption when
compared to conventional on-chip bus architectures. Recently, there has
been a great deal of interest in the development of run-time approaches for
reconfigurable NoC. These approaches provide techniques that allow NoC to
autonomously adapt its structure and its behavior to system changes.
The Workshop topics of interest include (but are not limited to) the
following:
? Topologies reconfiguration for NoC
? Routing algorithms, switching techniques, and flow control schemes
? Mapping and scheduling of tasks into NoC
? Self-reconfiguration and self-optimization of NoC
? Bio-inspired techniques for reconfigurable NoC
? Analytical evaluation methods for designing reconfigurable NoC
? Area, energy, and performance evaluation
? Tools for design space exploration of reconfigurable NoC
? Cases studies and FPGA-based implementation of reconfigurable NoC
Accepted papers will be published in the Conference proceedings.
Submission guidelines are available on the HPCS 2013 Conference web site at
http://hpcs2013.cisedu.info/. If you have any questions about paper
submission or the workshop, please contact the workshop organizers.
--DRNoC chairs
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