CALL FOR PAPERS
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2nd International Workshop on Exploiting Silicon Photonics for
energy-efficient high performance computing (SiPhotonics'2015), 19-21 January, 2015 Amsterdam, The Netherlands
http://www.hipeac.net/2015/ams
associated with the 10th HiPEAC conference on High Performance and Embedded Architecture and Compilers (http://www.hipeac.net/2015/am
******************************
Goal of the Workshop:
With Exascale systems on the horizon, we will be ushering in an era with power and energy consumption as the primary concerns for scalable computing. To achieve viable high performance, revolutionary methods are required with a stronger integration among hardware features, system software and applications.
The main purpose of this workshop is to promote further research interests and activities on Silicon Photonics and related topics in the perspective of its adoption in future high performance systems and, in general, within future computing systems (from servers/workstations down to embedded devices). In fact, Silicon Photonics poses in itself crucial challenges and interesting design tradeoffs for being deployed in future computer systems effectively, also in integration with other technologies. Furthermore, the unique features of photonics (e.g. extreme low-latency, end-to-end transmission, high bandwidth density) have the potential to constitute a discontinuity element able to modify the expected shape of future computer systems from the design point of view and also from the programmability and/or runtime management perspectives.
Summarizing, silicon photonics can bring innovations and benefits into current and foreseeable computing systems directly, due to their intrinsic features, but also indirectly enabling the evolution towards architectures, runtime and resource management approaches that maximize the photonic raw technological opportunities and lead to more efficient overall designs, otherwise impossible.
This workshop aims to increase the synergy from a complete range of perspectives, from raw technology issues and solutions up to studies at the overall system level of modern multi-/many-core systems, both from academic and industrial researchers working in this area. We are interested in experimental, systems-related, and work-in-progress papers in all aspects of the Silicon Photonics technology at all levels of development.
To emphasize both the fundamental impact of silicon photonic technologies on future system and interconnection network architectures and, conversely, the driving forces of practical and economically viable system-level design, requirements and constraints on the underlying technologies, this year the SiPhotonics and INA-OCMC Workshops will be held in a federated fashion. We plan to organize joint keynote presentations and a panel discussion with experts from both fields on topics of interest to both communities. This way, we intend to foster the exchange of ideas and increase collaboration between these highly complementary workshops. The paper submission and review processes will, however, still be run independently by each workshop.
Topics of interest:
Authors are invited to submit high quality papers representing original work from both the academia and industry in (but not limited to) the following topics:
- Photonics in the memory hierarchy and I/O of computing systems, QoS management and performance analysis. On-chip and inter-chip approaches
- Emerging challenges and solutions for on-chip interconnections, runtime and programmability for future homogeneous/heterogeneous CMPs
- Interaction of photonic features and opportunities with chip-multiprocessor architectural features, runtime and operating system
- Addressing thermal-/energy- and power-related issues
- Solving the requirements of multiple heterogeneous parallel applications
- Simulation, validation and verification
- Synergies and tradeoffs between photonic and electronic network technologies
- Low-level technological improvements and implications (e.g. integrated lasers, modulation and detection technologies, microring resonators) for computer system communication
- Industrial practices and case studies
Submission guidelines:
Prospective authors should submit electronically a full paper in English in PDF format. Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal.
All manuscripts will be reviewed and will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the workshop attendees.
They should be formatted according to the IEEE Conference proceedings format - http://www.ieee.org/conference
Submissions can be made through the submission web site at the IEEE CPS Web-based paper submission site.
Publication:
Informal proceedings will be provided in an USB stick to all participants including all material relevant to the conference and the related events.
The proceedings of the workshop will be published by the IEEE Computer Society's Conference Publishing Services (CPS)http://www.computer.org/portal
Registration:
Authors of accepted papers are expected to register and present their papers at the conference.
Important dates:
Paper submission deadline: November 15, 2014
Notification of acceptance: November 30, 2014
Camera-ready paper due: December 13, 2014
Conference: 19th - 21th January 2015
Co-chairs:
José M. García, University of Murcia, Spain.
Sandro Bartolini, University of Siena, Italy
Program committee:
Keren Bergman Columbia University
Giovanna Calo Politecnico di Bari
José M. Cecilia Catholic University of Murcia
Yawen Chen Otago University
Ricardo Fernández-Pascual University of Murcia
Pierfrancesco Foglia University of Pisa
Antonio Garcia-Guirado ARM Norway - NTNU
Paolo Grani University of Siena
Huaxi Gu Xidian University
Timothy Jones University of Cambridge
Kostas Katrinis IBM Ireland
Sébastien Le Beux Lyon Institute of Nanotechnology (INL)
Xavier Martorell Barcelona Supercomputing Center (BSC) & UPC
Gokhan Memik Northwestern University
Sergei Mingaleev VPIphotonics
Takahiro Nakamura Photonics Electronics Technology Research Association
Sudeep Pasricha Colorado State University
Luca Ramini University of Ferrara
Oded Raz COBRA Research Institute (Eindhoven University of Technology)
Marco Romagnoli CNIT
José Luis Sánchez University of Castilla-La Mancha
Laurent Schares IBM TJ Watson
Philip M. Watts University College London
Contacts:
Prof. José M. García
Departamento de Ingeniería y Tecnología de Computadores
University of Murcia, Spain.
email: jmgarcia[at]ditec.um.es
Tel.: +34 868 884819 Fax: +34 868 884151
Ing. Sandro Bartolini, PhD
Dipartimento di Ingegneria dell'Informazione e Scienze Matematiche
University of Siena, Italy
E-mail: bartolini[at]dii.unisi.it
Tel: +39 0577 234850 Fax: +39 0577 233609
--
-----------------------------
Prof. Jose Manuel Garcia Carrasco
Departamento de Ingenieria y Tecnologia de Computadores
Facultad de Informatica. Universidad de Murcia
Campus de Espinardo - 30080 Murcia (SPAIN)
Tel.: +34-868-884819 Fax: +34-868-884151
email: jmgarcia@ditec.um.es | jm.garcia@ieee.org
url: http://webs.um.es/jmgarcia
******************************
2nd International Workshop on Exploiting Silicon Photonics for
energy-efficient high performance computing (SiPhotonics'2015), 19-21 January, 2015 Amsterdam, The Netherlands
http://www.hipeac.net/2015/ams
associated with the 10th HiPEAC conference on High Performance and Embedded Architecture and Compilers (http://www.hipeac.net/2015/am
******************************
Goal of the Workshop:
With Exascale systems on the horizon, we will be ushering in an era with power and energy consumption as the primary concerns for scalable computing. To achieve viable high performance, revolutionary methods are required with a stronger integration among hardware features, system software and applications.
The main purpose of this workshop is to promote further research interests and activities on Silicon Photonics and related topics in the perspective of its adoption in future high performance systems and, in general, within future computing systems (from servers/workstations down to embedded devices). In fact, Silicon Photonics poses in itself crucial challenges and interesting design tradeoffs for being deployed in future computer systems effectively, also in integration with other technologies. Furthermore, the unique features of photonics (e.g. extreme low-latency, end-to-end transmission, high bandwidth density) have the potential to constitute a discontinuity element able to modify the expected shape of future computer systems from the design point of view and also from the programmability and/or runtime management perspectives.
Summarizing, silicon photonics can bring innovations and benefits into current and foreseeable computing systems directly, due to their intrinsic features, but also indirectly enabling the evolution towards architectures, runtime and resource management approaches that maximize the photonic raw technological opportunities and lead to more efficient overall designs, otherwise impossible.
This workshop aims to increase the synergy from a complete range of perspectives, from raw technology issues and solutions up to studies at the overall system level of modern multi-/many-core systems, both from academic and industrial researchers working in this area. We are interested in experimental, systems-related, and work-in-progress papers in all aspects of the Silicon Photonics technology at all levels of development.
To emphasize both the fundamental impact of silicon photonic technologies on future system and interconnection network architectures and, conversely, the driving forces of practical and economically viable system-level design, requirements and constraints on the underlying technologies, this year the SiPhotonics and INA-OCMC Workshops will be held in a federated fashion. We plan to organize joint keynote presentations and a panel discussion with experts from both fields on topics of interest to both communities. This way, we intend to foster the exchange of ideas and increase collaboration between these highly complementary workshops. The paper submission and review processes will, however, still be run independently by each workshop.
Topics of interest:
Authors are invited to submit high quality papers representing original work from both the academia and industry in (but not limited to) the following topics:
- Photonics in the memory hierarchy and I/O of computing systems, QoS management and performance analysis. On-chip and inter-chip approaches
- Emerging challenges and solutions for on-chip interconnections, runtime and programmability for future homogeneous/heterogeneous CMPs
- Interaction of photonic features and opportunities with chip-multiprocessor architectural features, runtime and operating system
- Addressing thermal-/energy- and power-related issues
- Solving the requirements of multiple heterogeneous parallel applications
- Simulation, validation and verification
- Synergies and tradeoffs between photonic and electronic network technologies
- Low-level technological improvements and implications (e.g. integrated lasers, modulation and detection technologies, microring resonators) for computer system communication
- Industrial practices and case studies
Submission guidelines:
Prospective authors should submit electronically a full paper in English in PDF format. Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal.
All manuscripts will be reviewed and will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the workshop attendees.
They should be formatted according to the IEEE Conference proceedings format - http://www.ieee.org/conference
Submissions can be made through the submission web site at the IEEE CPS Web-based paper submission site.
Publication:
Informal proceedings will be provided in an USB stick to all participants including all material relevant to the conference and the related events.
The proceedings of the workshop will be published by the IEEE Computer Society's Conference Publishing Services (CPS)http://www.computer.org/portal
Registration:
Authors of accepted papers are expected to register and present their papers at the conference.
Important dates:
Paper submission deadline: November 15, 2014
Notification of acceptance: November 30, 2014
Camera-ready paper due: December 13, 2014
Conference: 19th - 21th January 2015
Co-chairs:
José M. García, University of Murcia, Spain.
Sandro Bartolini, University of Siena, Italy
Program committee:
Keren Bergman Columbia University
Giovanna Calo Politecnico di Bari
José M. Cecilia Catholic University of Murcia
Yawen Chen Otago University
Ricardo Fernández-Pascual University of Murcia
Pierfrancesco Foglia University of Pisa
Antonio Garcia-Guirado ARM Norway - NTNU
Paolo Grani University of Siena
Huaxi Gu Xidian University
Timothy Jones University of Cambridge
Kostas Katrinis IBM Ireland
Sébastien Le Beux Lyon Institute of Nanotechnology (INL)
Xavier Martorell Barcelona Supercomputing Center (BSC) & UPC
Gokhan Memik Northwestern University
Sergei Mingaleev VPIphotonics
Takahiro Nakamura Photonics Electronics Technology Research Association
Sudeep Pasricha Colorado State University
Luca Ramini University of Ferrara
Oded Raz COBRA Research Institute (Eindhoven University of Technology)
Marco Romagnoli CNIT
José Luis Sánchez University of Castilla-La Mancha
Laurent Schares IBM TJ Watson
Philip M. Watts University College London
Contacts:
Prof. José M. García
Departamento de Ingeniería y Tecnología de Computadores
University of Murcia, Spain.
email: jmgarcia[at]ditec.um.es
Tel.: +34 868 884819 Fax: +34 868 884151
Ing. Sandro Bartolini, PhD
Dipartimento di Ingegneria dell'Informazione e Scienze Matematiche
University of Siena, Italy
E-mail: bartolini[at]dii.unisi.it
Tel: +39 0577 234850 Fax: +39 0577 233609
--
-----------------------------
Prof. Jose Manuel Garcia Carrasco
Departamento de Ingenieria y Tecnologia de Computadores
Facultad de Informatica. Universidad de Murcia
Campus de Espinardo - 30080 Murcia (SPAIN)
Tel.: +34-868-884819 Fax: +34-868-884151
email: jmgarcia@ditec.um.es | jm.garcia@ieee.org
url: http://webs.um.es/jmgarcia
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