Energy Efficient SuperComputing (E2SC)

2nd International Workshop on

                    Energy Efficient SuperComputing (E2SC)

         Held in conjunction with SC'14, New Orleans, Louisiana, USA
                           November 16th-21st 2014

                               Call for Papers


Description
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With Exascale systems on the horizon, we will be ushering in an era with power
and energy consumption as the primary concerns for scalable computing. To
achieve viable high performance, revolutionary methods are required with a
stronger integration among hardware features, system software and applications.
Equally important are the capabilities for fine-grained spatial and temporal
measurement and control to facilitate energy efficient computing across
all layers. Current approaches for energy efficient computing rely heavily on
power efficient hardware in isolation. However, it is pivotal for hardware to
expose mechanisms for energy efficiency to optimize power and energy
consumption for various workloads and to reduce data motion, a major component
of energy use. At the same time, high fidelity measurement techniques,
typically ignored in data-center level measurement, are of high importance
for scalable and energy efficient inter-play in different layers of
application, system software and hardware.

This workshop seeks to address the important energy efficiency aspects in the
HPC community that have not been previously addressed by aspects covered in
the data center or cloud computing communities. Emphasis is given to the
applications view related to significant energy efficiency improvements and
to the required hardware/software stack that must include necessary power and
performance measurement and analysis harnesses.

Current tools are often limited by hardware capabilities and their lack of
information about the characteristics of a given workload/application. In the
same manner, hardware techniques, like dynamic voltage frequency scaling, are
often limited by their granularity (very coarse power management) or by their
scope (a very limited system view). More rapid realization of energy savings
will require significant increases in measurement resolution and optimization
techniques.  Moreover, the interplay between performance, power and
reliability add another layer of complexity to this already difficult group
of challenges.


Workshop Focus
--------------

We encourage submissions in the following areas:

- Tools for analyzing power and energy with different granularities and
  scope from hardware (e.g., component, core, node, rack, system) or
  software views (e.g., threads, tasks, processes, etc.) or both.
- Tools and techniques for measurement, analysis, and modeling of thermal
  effects at different granularities (e.g., component, core, node, rack,
  system) for large-scale systems.
- Techniques that enable power and energy optimizations at different
  scale levels for HPC systems.
- Integration of power-aware technologies in applications and throughout
  the software stack of HPC systems.
- Characterization of current state-of-the-art HPC systems and
  applications in terms of power.
- Disruptive hardware of infrastructure technologies for energy-efficient
  supercomputing.
- Analysis of future technologies that will provide improved energy
  consumption and management on future HPC systems.


Organizing Committee
--------------------

General Chairs:       Kirk Cameron, Virginia Tech, USA
                      Adolfy Hoisie, Pacific Northwest National Laboratory, USA
                      Darren Kerbyson, Pacific Northwest National Laboratory, USA
                      David Lowenthal, Arizona State University, USA
                      Dimitrios S. Nikolopoulos, Queen's University of Belfast, UK
                      Sudha Yalamanchili, Georgia Institute of Technology, USA
Program Chair:        Andres Marquez, Pacific Northwest National Laboratory, USA
Publicity Chair:      Kevin J. Barker, Pacific Northwest National Laboratory, USA
European Liaison:     Michele Weiland, EPCC, UK
Publication Chair:    Abhinav Vishnu, Pacific Northwest National Laboratory, USA
Onsite Coordination:  Joseph Manzano, Pacific Northwest National Laboratory, USA


Program Committee
-----------------

Avram Bar-Cohen         DARPA-MTO, USA
Laura Carrington        San Diego Supercomputing Center, USA
Sunita Chandrasekaran   University of Houston, USA
Paul Franzon            North Carolina State University, USA
Roberto Gioiosa         Pacific Northwest National Laboratory, USA
Georg Hager             Erlangen Regional Computing Center, Germany
Karen Karavanic         Portland State University, USA
Hyesoon Kim             Georgia Institute of Technology, USA
Dong Li                 Oak Ridge National Laboratory, USA
Sheng Li                Intel, USA
Benoit Meister          Reservoir Labs, USA
Leonid Oliker           Lawrence Berkeley National Laboratory, USA
Barry Rountree          Lawrence Livermore National Laboratory, USA
Vijay Reddi             University of Texas at Austin, USA
Sameer Shende           University of Oregon, USA
Shuaiwen Leon Song      Pacific Northwest National Laboratory, USA
Eric Van Hensbergen     ARM Research, USA


Important Dates
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Paper Submission        24th August 2014
Paper Notification      25th September 2014
Final Papers Due        10th October 2014


Submission Guidelines
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Papers should not exceed eight single-space pages (including figures, tables
and references) using a 12-point on 8.5x11-inch pages. Submissions will be
judged on correctness, originality, technical strength, significance,
presentation quality and appropriateness. Submitted papers should not have
appeared in or under consideration for another venue. A full peer-review
processes will be followed with each paper being reviewed by at least 3
members of the program committee. Submissions will be made through EasyChair
(http://www.easychair.org<http://www.easychair.org/>)