[Apologies if you got multiple copies of this email. This message is
sent to . If you'd like to opt out of these
announcements, information on how to unsubscribe is available at the
bottom of this email.]
CALL FOR PARTICIPATIONFriday, Nov 18, 2016 from 8:30am-12:10 p.m. in room 355-D(please check http://software.intel. com/en-us/event/comhpc/2016/ overview for more details about the workshop)
****************************** ****************************** ********************
(https://lists.mcs.anl.gov/ mailman/listinfo/hpc-announce
If you do not remember your password (which is needed to change these options), you can reset it using the "Unsubscribe or Edit Options" button at the bottom of the page.
(https://lists.mcs.anl.gov/ mailman/listinfo/hpc-announce)
.
****************************** ****************************** ********************
sent to . If you'd like to opt out of these
announcements, information on how to unsubscribe is available at the
bottom of this email.]
First International Workshop on Communication Optimizations in HPC (COMHPC)
In cooperation with ACM SIGHPC
co-located with
CALL FOR PARTICIPATIONFriday, Nov 18, 2016 from 8:30am-12:10 p.m. in room 355-D(please check http://software.intel.
Workshop Program
8:30 – 9:15
|
Keynote: Bill Gropp (NCSA, UIUC) – Meeting the Communication Needs of Scalable Applications
|
9:15 – 10:05
|
Technical Session 1:
|
9:15
|
Efficient Reliability Support for Hardware Multicast-based Broadcast in GPU-enabled Streaming Applications
|
9:35
|
Topology and affinity aware hierarchical and distributed load-balancing in Charm++
|
9:55
|
Extending a Message Passing Runtime to Support Partitioned, Global Logical Address Spaces
|
10:05 – 10:30
|
Coffee break
|
10:30 – 12:10
|
Technical Session 2:
|
10:30
|
DISP: Optimizations towards Scalable MPI Startup
|
10:50
|
Network Topologies and Inevitable Contention
|
11:10
|
Topology-Aware Data Aggregation for Intensive I/O on Large-Scale Supercomputers
|
11:30
|
Scalable Hierarchical Aggregation Protocol SHArP: A Hardware Architecture for Efficient Data Reduction
|
11:50
|
Topology-Aware Performance Optimization and Modeling of Adaptive Mesh Refinement Codes for Exascale
|
As HPC applications scale to large super-computing systems, their communication and synchronization need to be optimized in order to deliver high performance. To achieve this, capabilities of modern network interconnect and parallel runtime systems need to be advanced and the existing ones to be leveraged optimally. Participants at this workshop will benefit from discussions, collaboration, and ideas that drive the design of future peta/exa-scale systems and HPC applications.
Organizing Committee:
- Michael Chuvelev (Intel, Russia)
- Daniel Faraj (SGI, USA)
- Maria Garzaran (UIUC and Intel, USA)
- Akhil Langer (Intel, USA)
- Malek Musleh (Intel USA)
- Gengbin Zheng (Intel, USA)
Program Committee:
- Ahmad Afsahi (Queen’s University, Canada)
- George Almasi (IBM, USA)
- Abhinav Bhatele (LLNL, USA)
- Bill Gropp (University of Illinois Urbana-Champaign, USA)
- Manish Gupta (Xerox Research Center, India)
- Ram Huggahalli (Intel, USA)
- Nikhil Jain (LLNL, USA)
- David Lowenthal (University of Arizona, USA)
- Vijay Pai (Google, USA)
- D. K. Panda (Ohio State University, USA)
- Sameh Sharkawi (IBM, USA)
- Yogish Sabharwal (IBM, India)
- Martin Schulz (LLNL, USA)
- Bronis R. de Supinski (LLNL, USA)
- Sayantan Sur (Intel, USA)
- Michela Taufer (University of Delaware, USA)
- Keith Underwood (Intel, USA)
- Abhinav Vishnu (PNNL, USA)
- Alan Wagner (University of British Columbia, Canada)
- Xin Yuan (Florida State University, USA)
Contact:
******************************
(https://lists.mcs.anl.gov/
If you do not remember your password (which is needed to change these options), you can reset it using the "Unsubscribe or Edit Options" button at the bottom of the page.
(https://lists.mcs.anl.gov/
******************************
No comments:
Post a Comment